Sub-nm High Performance Color Video Codec System for Emergency Medicine and Preventing Disaster

1.研究了运动图像编解码、高速信号处理、低功耗、低漏电流等关键技术。各种高速运动矢量估计方法已被开发出来。为了降低视频编解码处理器的功耗，提出了一种基于自适应分配中断条件搜索(AABCS)算法的快速运动估计算法。AABCS在保持全搜索方法视觉质量的同时，可以将传统的全搜索方法的处理速度提高50倍以上。在160MHZ的时钟频率和1.0V的电源电压下，采用AABCS和门控时钟脉冲方案的90 nm视频编解码器的功耗降低到20μW，约为相同实现传统FS方法的编解码器的1/100。为了同时降低泄漏电流和动态功率，设计了一种可根据要求向有源负载电路提供最大直流电压或在待机模式下降低负载电路直流电压的自控电压电平电路。该SVL电路以最小的芯片面积和速度大大降低了芯片的备用漏电功耗。采用SVL电路的2kBSRAM的待机功率为1.4 mW，约为传统2kbit SRAM的4.9%。这种新型SRAM的有功功率为620 mW，相当于传统2kbit SRAM的28.8%。这种新的SRAM的读访问时间为553PSEC，仅比同等的传统1KB SRAM长2.6%。

1. Related technologies for this research such as moving picture encoding and decoding, high speed signal processing, low-power and low-leakages current for LSIs, etc have been investigated.2. Various high speed motion vector estimation methods have been developed. To reduce power dissipation of video codec processors, a fast ME algorithm called a fast motion estimation algorithm employing adaptively assigned breaking-off condition search (AABCS) algorithm was developed. AABCS can improve processing speed of the conventional full-search (FS) method by a factor of more than 50, while maintaining visual quality of the FS method.3. At clock frequency of 160 MHz and supply voltage of 1.0 V the power dissipation of a developed 90-nm CMOS video codec processor using AABCS and a gated-clock pulse scheme was reduced to 20 μW that was about 1/100 that of the same codec processor implementing a conventional FS method.4. In order to reduce both leakage current and dynamic power, a self-controllable voltage level (SVL) circuit, which can supply a maximum DC voltage to an active-load circuit on request or can decrease the DC voltage supplied to a load circuit in stand-by mode, was developed. This SVL circuit can drastically reduce stand-by leakage power of CMOS logic circuits and SRAMs with minimal overheads in terms of chip area and speed. The stand-by power of 2-Kb SRAM incorporating the SVL circuit was 1.4 mW that was about 4.9% of that of an equivalent conventional 2-Kbit SRAM. The active power of this new SRAM was 620 mW, 28.8% of that of the equivalent conventional 2-Kbit SRAM. The read-access time of this new SRAM was 553 psec, that is, only 2.6% longer than that of the equivalent conventional 1-Kb SRAM.