Sub-nm High Performance Color Video Codec System for Emergency Medicine and Preventing Disaster

1.研究了运动图像编解码、高速信号处理、LSI的低功耗和低漏电流等相关技术.已经开发了各种高速运动矢量估计方法。为了降低视频编解码处理器的功耗，提出了一种基于自适应中断条件搜索（AABCS）的快速运动估计算法。AABCS可以在保持FS方法视觉质量的同时，将传统的全搜索（FS）方法的处理速度提高50倍以上.在时钟频率为160 MHz，电源电压为1.0 V时，采用AABCS和门控时钟脉冲方案的90 nm CMOS视频编解码处理器的功耗降低到20 μW，约为采用传统FS方法的相同编解码处理器的1/100.为了降低漏电流和动态功耗，设计了一种可根据需要向有源电路提供最大直流电压或在待机模式下降低向负载电路提供的直流电压的电压电平自控制电路。该SVL电路可以在芯片面积和速度方面以最小的开销大幅降低CMOS逻辑电路和SRAM的待机泄漏功率。采用SVL电路的2-Kb SRAM的待机功率为1.4 mW，约为等效的传统2-Kbit SRAM的待机功率的4.9%。这种新型SRAM的有效功率为620 mW，是传统2-Kbit SRAM的28.8%。这种新型SRAM的读访问时间为553 psec，仅比同等的传统1-Kb SRAM长2.6%。

1. Related technologies for this research such as moving picture encoding and decoding, high speed signal processing, low-power and low-leakages current for LSIs, etc have been investigated.2. Various high speed motion vector estimation methods have been developed. To reduce power dissipation of video codec processors, a fast ME algorithm called a fast motion estimation algorithm employing adaptively assigned breaking-off condition search (AABCS) algorithm was developed. AABCS can improve processing speed of the conventional full-search (FS) method by a factor of more than 50, while maintaining visual quality of the FS method.3. At clock frequency of 160 MHz and supply voltage of 1.0 V the power dissipation of a developed 90-nm CMOS video codec processor using AABCS and a gated-clock pulse scheme was reduced to 20 μW that was about 1/100 that of the same codec processor implementing a conventional FS method.4. In order to reduce both leakage current and dynamic power, a self-controllable voltage level (SVL) circuit, which can supply a maximum DC voltage to an active-load circuit on request or can decrease the DC voltage supplied to a load circuit in stand-by mode, was developed. This SVL circuit can drastically reduce stand-by leakage power of CMOS logic circuits and SRAMs with minimal overheads in terms of chip area and speed. The stand-by power of 2-Kb SRAM incorporating the SVL circuit was 1.4 mW that was about 4.9% of that of an equivalent conventional 2-Kbit SRAM. The active power of this new SRAM was 620 mW, 28.8% of that of the equivalent conventional 2-Kbit SRAM. The read-access time of this new SRAM was 553 psec, that is, only 2.6% longer than that of the equivalent conventional 1-Kb SRAM.