High-Level Synthesis of VLSI Processors Based on Logic-in-Memory Architecture

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One of the most serious problem in recent VLSI system is data transfer bottleneck between memories and processing elements. To solve the problem, a model of highly parallel VLSI processor is presented. A logic-in-memory module composed of a processing element, a register and a local memory is defined as a basic building block to form a regular parallel structure. The data transfers between adjacent modules are done simply in a single clock period by a shift-register chain.A high-level synthesis method is discussed on the hardware model, when a data-dependency graph corresponding to a processing algorithm is given. We must simultaneously consider both scheduling and allocation for the time optimization problem under a constraint of a chip area. That is, we consider the best scheduling together with allocation such that the processing time become minimum under a constraint of a fixed number of modules. A genetic algorithm and a heuristic algorithm are proposed for the problem. As a result, it is made clear that the proposed high-level synthesis method is very effective to design special-purpose VLSI processors free from data transfer bottleneck.