Self-Timed High-Performance Real-time Processing Architecture

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The objective of this research project is to establish a high-performance network processor architecture based on the fully self-timed pipeline scheme. The following research results are obtained during the project. Next-generation high-speed network processors are required to achieve high-speed packet forwarding, to introduce new protocols and highly functional network services, and also to save electric power along with effective processing rate. The self-timed superpipelined data-driven architecture is one of the most promising architectures to satisfy these requirements because it is able to realize highly-functional and complex tasks by ultra-parallel processing software executable on flexible pipelined hardware.(a)High-speed packet classification scheme Packet classification is one of heavy tasks in high-speed internet routers. We proposed a super-pipelined packet classification scheme. By using this scheme, we can classify about 12 M packets/second even in large scale internet exchange nodes having over 100 k classification rules.(b)Priority based queueing scheme applicable to Diffserv The self-timed pipeline scheme is capable to realize high functionalities on silicon by virtue of its localized control. We proposed a priority-based queueing scheme as a highly-functional application of the self-timed pipeline scheme. A 0.18 um CMOS prototype chip of the proposed scheme using a folded self-timed pipeline structure was capable to queue and schedule 100 M packets/second autonomously.