Ultra-wideband highly linear Sampler and Analog-to-Digital Converter – DISCO

本研究提案针对超高速、宽带模数转换器（ADC）架构领域，其采样速率为128 GS/s及以上，目标奈奎斯特信号带宽至少为60 GHz，同时保持有效位数（ENOB）大于6，以实现下一代光纤，雷达和无线通信系统的数据速率超过200 GBit/s每波长。为了解决这些具有挑战性的性能指标，时间交织输入缓冲电感峰值跟踪和保持（T/H）拓扑结构的研究，它适用于一种新的主动批量调制技术。该架构利用现代全耗尽绝缘体上硅（FDSOI）技术的增强背栅能力来实现有源负反馈体调制方案，从而显著增强可获得的带宽，同时改善前端线性度。与最先进的CMOS和SiGe BiCMOS方法相比，这实现了单片集成，并显著降低了功耗问题。对于以下ADC内核，提出了闪存和逐次逼近寄存器（SAR）-ADC的组合，从而结合了两者的优点，即闪存-ADC在单个时钟周期内转换多个位，SAR ADC的固有功耗和面积效率，在两步子ADC通道中。此外，所提出的SAR-ADC利用先进的环路展开拓扑实现超快转换时间。此外，现有的带宽限制，以及时间交织的样本相位失配进行了分析，建模和校准使用混合信号的方法，即。e.基于功率高效数字相关的带宽和相位误差估计，同时使用创新的模拟校正和亚毫微微法拉电容调谐，实现数十飞秒范围内的相移。这些创新的成功结合将为信噪比（SNR）、无杂散动态范围（SFDR）采样率和信号带宽，同时与当前最先进的技术相比提高了功率效率，产生了突出的科技成果潜力。

This research proposal addresses the field of ultra-high-speed, wideband analog-to-digital converter (ADC) architectures with sample rates of 128 GS/s and beyond with target Nyquist signal bandwidth of at least 60 GHz while maintaining an effective number of bits (ENOB) of more than 6 to enable the next generation of fiber optics, radar and wireless communication systems with data rates of beyond 200 GBit/s per wavelength. To address these challenging performance metrics, a time-interleaved input-buffered inductively peaked track-and-hold (T/H) topology is investigated which applies a novel active bulk modulation technique. The architecture makes use of the enhanced back-gate capabilities of modern fully depleted silicon-on-insulator (FDSOI) technologies to implement an active negative-feedback bulk modulation scheme, thereby significantly enhancing the obtainable bandwidth while improving the front-end linearity at the same time. This enables monolithic integration and significantly reduced power concerns compared to state-of-the-art CMOS and SiGe BiCMOS approaches.For the following ADC core, a combination of Flash- and successive-approximation-register (SAR)-ADC is proposed, thereby combining the benefits of both, namely the conversion of multiple bits in a single clock cycle of the Flash-ADC and the SAR ADCs native power and area efficiency, in a two-step sub-ADC lane. Furthermore, the proposed SAR-ADC takes advantage of an advanced loop-unrolled topology to achieve ultra-fast conversion times. In addition, existing bandwidth limitations as well as time-interleaved sample phase mismatches are analyzed, modelled and calibrated using a mixed-signal approach, i. e. power-efficient digital correlation-based estimation of the bandwidth- and phase-errors while using an innovative analog correction with sub-femtofarad capacitor-tuning achieving phase shifts in the range of tens of femtoseconds.Successfully combining these innovations will open the door for significant performance improvements in terms of signal-to-noise ratio (SNR), spurious free dynamic range (SFDR), sample rate and signal bandwidth while at the same time improving the power efficiency compared to the current state-of-the-art, yielding outstanding potential for scientific and technological achievements.