Development of ASIC Design Support System
Development of ASIC Design Support System
批准号:
05558031
负责人:
TANIGUCHI Kenichi
金额:
$2.5万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for Developmental Scientific Research (B)
财政年份:
1993
资助国家:
日本
项目状态:
已结题
起止时间:
1993 至 1994
中文摘要
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英文摘要
(1) For designing high reliable ASIC's (Application Specific IC's) , it is important that we can prove the correctness of implementations formally and that we can automate some design steps. In this research, we have proposed a design methodology to develop correct ASIC's and developed a design support system.(2) In the proposed method, we design ASIC's as follows.(a) First, we describe an abstract level's specification using our algebraic specification language ASL,and then we refine the specification into more concrete levels'specifications step by step.(b) To prove the correctness of each design step efficiently, we have developed a verifier. We restrict the style of descriptions. The verifier has an efficient decision procedure for prenex normal form Presburger sentences bounded by only universal quantifiers. In our method, the designer only gives assertions and some theorems for primitives. Then, the verifier mechanically checks whether the given assertions hold as invariants.(c) In general, to improve the efficiency of circuits, we need transform a state diagram obtained the above step. We have given some transformation rules. We have also developed an interactive transformation support tool.(d) Finally, we use our circuit generator to obtain a concrete circuit diagram. The circuit generator transforms the obtained state diagram into a SFL description and generates a concrete circuit using the synthesizer PARTHENON developed in NTT Corp., Japan.Our design support system consists of the above verifier, interactive transformation support tool and circuit generator.(3) We have evaluated the usefulness of our approach using some practical examples such as CPU and sort circuits.
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村上尚,北道淳司,森岡澄夫,西川清史,谷口健一: ""代数的手法を用いた同期式順序回路の設計支援機能の統合"" 1995年電子情報通信学会春期大会(A121). 基礎/境界. 121- (1995)
Hisashi Murakami、Junji Kitamichi、Sumio Morioka、Kiyoshi Nishikawa、Kenichi Taniguchi:“使用代数方法集成同步时序电路的设计支持功能”1995 IEICE 春季会议 (A121) (1995)。
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Sumio Morioka, Junji Kitamichi, Higasino Teruo and Kenichi Taniguchi: ""Facilities for State Diagran Transformation in Hardware Design Support System based on Algebraic Method"" Proceedings of the 8th Karuizawa Workshop on Circuits and Systems. (1995)
Sumio Morioka、Junji Kitamichi、Higasino Teruo 和 Kenichi Taniguchi:“基于代数方法的硬件设计支持系统中的状态图变换设施”第 8 届轻井泽电路与系统研讨会论文集。
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森岡澄夫,北道淳司,東野輝夫,谷口健一: ""整数上の論理式の恒真性判定アルゴリズムを用いた組合せ論理回路の実現の正しさの証明"" 情報処理学会第49回全国大会(4L-01). Vol.6. 87-88 (1994)
Sumio Morioka、Junji Kitamichi、Teruo Higashino、Kenichi Taniguchi:“使用确定整数逻辑公式恒常性的算法实现组合逻辑电路的正确性证明”日本信息处理学会第 49 届全国大会 (4L-01)。第6卷。87-88(1994)
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北嶋暁,森岡澄夫,北道淳司,東野輝夫,谷口健一: ""代数的言語ASLによる回路設計支援システムにおけるAFL記述への詳細化とその変更およびそれらの正しさの検証"" 情報処理学会第49回全国大会(4L-07). Vol.6. 99-100 (1994)
Akira Kitajima、Sumio Morioka、Junji Kitamichi、Teruo Higashino、Kenichi Taniguchi:“使用代数语言 ASL 对电路设计支持系统中的 AFL 描述进行细化和修改,并验证其正确性”日本信息处理学会第 49 届全国大会(4L-07)。第6卷99-100(1994)。
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Kenichi Taniguchi and Junji Kitamichi: ""Design and Verification of Sequential Logic Circuits Based on Algebraic Technique"" Transactions of the Information Processing Japan. Vol.35No.8. 742-750 (1994)
Kenichi Taniguchi 和 Junji Kitamichi:“基于代数技术的时序逻辑电路的设计和验证”,日本信息处理学报。
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共 28 条
Specification for Object-Oriented Software and Derivation of Programs
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批准号:13680414
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项目类别:Grant-in-Aid for Scientific Research (C)
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资助金额:$2.18万
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财政年份:2001
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负责人:TANIGUCHI Kenichi
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依托单位:
"Implementation of LOTOS specifications on distributed environments"
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批准号:10558046
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项目类别:Grant-in-Aid for Scientific Research (B).
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资助金额:$3.84万
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财政年份:1998
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负责人:TANIGUCHI Kenichi
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依托单位:
Hardware syntesis from formal descriptions of communication prorocols
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批准号:09680339
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项目类别:Grant-in-Aid for Scientific Research (C)
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资助金额:$1.98万
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财政年份:1997
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负责人:TANIGUCHI Kenichi
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依托单位:
海外基金