Hardware syntesis from formal descriptions of communication prorocols

本文提出了一种LOTOS协议规范的硬件实现技术，定义了一种新的同步EFSM模型，该模型由并发EFSM及其子集之间的有限个多重访问指示组成，用VHDL语言描述的同步EFSM可以很容易地实现为一个同步时序电路，通过将该技术应用于Abracadabra协议和一个简单的网络交换机，证实了该电路能有效地处理多个交会。

In this research, we propose a technique for hardware implementation of protocol specifications in LOTOS.For the purpose, we define a new model called synchronous EFSMs consisting of concurrent EFSMs and a finite set of multi-redezvous indications among their subsets, and propose a conversion algorithm from a subset of LOTOS.The derived synchronous EFSMs described in VHDL can be easily implemented as a synchronous sequential circuit where all the modules corresponding to the EFSMs work synchronously with the same clock.By applying our technique to the Abracadabra protocol and a sinple network switch, it is confirmed that the derived circuit handles multi-rendezvous efficiently.