ARCHITECTURE LEVEL DESIGN OPTIMIZATION METHODS FOR MICROPROCESSORS

微处理器架构级设计优化方法

• 批准号: 07680353
• 负责人: IMAI Masaharu
• 金额: $ 1.47万
• 依托单位: Osaka University (1996-1997)Toyohashi University of Technology (1995)
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (C)
• 财政年份: 1995
• 资助国家: 日本
• 起止时间: 1995 至 1997
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-07680353/
• 关键词: PIPELINE; PROCESSOR MODEL; VLIW PROCESSOR; GUI; ASIP; パイプライン・アーキテクチャ; 機能分割; 最適化設計; PEAS-I

Architecture optimization problems have been categorized into three types :(a) Performance maximization problem is to minimize the number of execution cycles under the constraints of chip area and power consumption. This problem is to be solved when a high performance processor is designed, fore example.(b) Area minimization problem is to minimize the chip area under the constraints of performance (execution cycles) and power consumption. This problem is to be solved when a hard read-time system is designed, for example.(c) Power consumption minimization problem is to minimizes the power consumption of the chip under the constrains of performance and power consumption. This problem is to be solved when a battery driven system is to be designed, for example.In this research, performance maximization problem and area minimization problem have been formalized as integer programming problems, then algorithms to solve these problems have been developed. All of these algorithms are based on the branch-and-bound method. Following algorithms have been developed.(1) Performance maximization algorithm for scalar (pipeline) type processor(2) Performance maximization algorithm for scalar (pipeline) type processor with consideration of the number of registers in CPU(3) Performance maximization algorithm for scalar (pipeline) type processor with consideration of the amount of on-chip memories (RAM and ROM)(4) Performance maximization algorithm for VLIW (pipeline) type processor with consideration of the amount of on-chip memories (RAM and ROM)(5)Area minimization algorithm for scalar (pipeline) type processorThe effectiveness and efficiency of these algorithms have been investigated through various kinds of application programs including digital signal processing.

体系结构优化问题分为三类：（1）性能最大化问题是在芯片面积和功耗的约束下，最小化执行周期的数量。这是设计高性能处理器时必须解决的问题。(b)面积最小化问题是在性能（执行周期）和功耗的约束下，使芯片面积最小。例如，当设计硬读取时间系统时，这个问题将被解决。(c)功耗最小化问题就是在满足性能和功耗的约束下，使芯片的功耗最小。在本研究中，将性能最大化问题和面积最小化问题形式化为整数规划问题，并提出了求解这些问题的算法。所有这些算法都是基于分支定界方法。已经开发了以下算法。(1)标量的性能最大化算法（2）标量的性能最大化算法考虑CPU寄存器数的流水线型处理器（3）标量性能最大化算法考虑片上存储器数量的（流水线）型处理器（4）VLIW的性能最大化算法考虑片上存储器数量的（流水线）型处理器（RAM和ROM）（5）标量（流水线）型处理器的面积最小化算法这些算法的有效性和效率已经通过包括数字信号处理在内的各种应用程序进行了研究。

项目成果

N.N.Binh, M.Imai, A.Shiomi, N.Hikichi: "An Instruction Set Optimization Algorithm for Pipelined ASIPs" IEICE Trans. Fundamentals. Vol.E78-A,No.12. 1707-1714 (1995)

N.N.Binh、M.Imai、A.Shiomi、N.Hikichi：“流水线 ASIP 的指令集优化算法”IEICE Trans。

N.Ohtsuki, Y.Takeuchi, M.Imai, K.Hamaguchi, T.Kashiwabara, N.Hikichi: "A Functional Unit Configuration Optimizing Method for VLIW Processor Design Automation" Technical Report of IEICE. VLD97-92. 101-108 (1997)

N.Ohtsuki、Y.Takeuchi、M.Imai、K.Hamaguchi、T.Kashiwabara、N.Hikichi：“一种用于 VLIW 处理器设计自动化的功能单元配置优化方法”IEICE 技术报告。

大槻 典正, 武内 良典, 今井 正治, 引地 信之: "VLIWプロセッサ生成系とVLIWコンパイラ生成系" 電子情報通信学会,基礎・境界ソサイエティ大会論文集. (1997)

Norimasa Otsuki、Yoshinori Takeuchi、Masaharu Imai、Nobuyuki Hikichi：“VLIW 处理器生成系统和 VLIW 编译器生成系统”IEICE 基础与边界学会会议记录（1997 年）。

大槻 典正, 武内 良典, 今井 正治, 浜口 清治, 柏原 敏伸, 引地 信之: "VLIWプロセッサ自動生成における演算器構成最適化の一手法" 信学技報(VLSI設計). Vol.97. 101-108 (1997)

Norimasa Otsuki、Yoshinori Takeuchi、Masaharu Imai、Seiji Hamaguchi、Toshinobu Kashihara、Nobuyuki Hikichi：“一种优化自动 VLIW 处理器生成中算术单元配置的方法”IEICE 技术报告（VLSI 设计）（1997 年）。 ）

N.N.Binh,M.Imai,A.Shiomi and N.Hikichi: "A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts" Proc.of the 33rd Design Automation Conference(DAC'96). (Accepted). (1996)

N.N.Binh、M.Imai、A.Shiomi 和 N.Hikichi：“用于设计具有最少门数的流水线 ASIP 的硬件/软件分区算法”第 33 届设计自动化会议 (DAC96) 的会议记录。