DEVELOPMENT OF MICROPROCESSOR ARCHITECURE DESIGN EDUCATION ENVIRONMENT

我们已经进行了研究的配置的微处理器设计教育环境，并开发了一个原型环境。（1）体系结构信息管理方法提出了一种适用于深亚微米工艺下“设计结果重用”、“面向重用的设计”和体系结构设计的硬件模型FHM（Flexible Hardware Model）。在此基础上，确定了FHM数据库管理系统（DBMS）的规范，并开发了一个原型系统。最后，利用数字滤波器（FIR滤波器）和其他数字信号处理模块（DCT）对原型系统进行了设计实验。(2)体系结构信息的描述和输入方法首先，体系结构信息已经被分类，以便可以处理各种类型的处理器。然后确定必要的结构参数来描述弧 关于我们 体系结构接下来，GUI（图形用户界面）已被设计成输入/编辑/显示之间的设计师和系统的架构参数。(3)硬件描述的生成方法硬件描述语言（HDL）的处理器描述的生成算法已经开发。一个是适合于高速模拟和其他的是适合于逻辑综合产生的描述。研究了从处理器的“行为语义描述”生成HDL描述的另一种方法。(4)Optimization Assistant Environment各种体系结构级优化算法已经开发出来。它们中的一些能够通过考虑（a）CPU中的寄存器的数量;（B）片上存储器（RAM和ROM）的数量来调整处理器的指令集，从而最小化应用程序的执行周期。另一种算法是通过调整功能单元的种类和数量来最小化VLIW（超长指令集）类型CPU核的执行周期。(5)应用程序开发环境生成器生成器和指令集级模拟器生成器已分别为标量（流水线）型CPU和VLIW型CPU核开发。这些生成器接受架构参数，如功能单元的种类和数量，寄存器的数量。生成的编译器将用于性能评估以及为生成的CPU核心生成目标代码。少

We have performed a study on the configuration of the microprocessor design education environment and developed a prototype of the environment. Major research topics performed in this research are as follows :(1) Architecture Information Management MethodA hardware model named FHM (Flexible Hardware Model) has been proposed, which is suitable for "reuse of design results", "design for reuse", and architecture design in the deep sub-micron technology. Then the specification of a database management system (DBMS) for FHM has been decided, and a prototype of FHM-DBMS has been developed. Finally, the prototype system has been evaluated through the design experiments using digital filters (FIR filters) and other digital signal processing module (DCT).(2) Description and Input Methods of Architecture InformationFirst, architecture information has been classified so that various types of processors can be handled. Then necessary architecture parameters have been identified to describe the arc … More hitecture. Next a GUI (Graphical User Interface) has been designed to input/edit/display architecture parameters between a designer and the system.(3) Generation Method of Hardware DescriptionAlgorithms to generate HDL (hardware description language) descriptions of processors have been developed. One of the yielded descriptions is suitable for high-speed simulation and the other is suitable for logic synthesis. Another approach to generate HDL description from "behavioral semantic description" of a processor was also investigated.(4) Optimization Assistant EnvironmentVarious architectural level optimization algorithms have been developed. Some of them are able to minimize execution cycles of application programs by adjusting the instruction set of the processor with consideration of (a) number of registers in CPU ; (b) amount of on-chip memories (RAM and ROM). Another algorithm is able to minimize execution cycles of VLIW (Very Long Instruction Set) type CPU core by adjusting the kinds and number of functional units.(5) Application Program Development Environment GenerationCompiler generators and instruction set level simulator generators have been developed for scalar (pipeline) type CPU and VLIW type CPU core, respectively. These generators accept architecture parameters such as kinds and number of functional units, number of registers. Yielded compilers are to be used for performance estimation as well as object code generation for the generated CPU core. Less