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Studies on hardware algorithms for high-performance arithmetic circuits

高性能运算电路的硬件算法研究

基本信息

批准号：
10680349
负责人：
TAKAGI Naofumi
金额：
$ 1.98万
依托单位：
Nagoya University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (C)
财政年份：
1998
资助国家：
日本
起止时间：
1998 至 2000
项目状态：
已结题

项目摘要

1. We have developed a hardware algorithm for computing the Euclidean norm of a 3D vector which often appears in 3D computer graphics, and designed and implemented an LSI based on it.2. We have developed a hardware algorithm for cube rooting which appears in computer graphics, and designed and implemented an LSI based on it.3. We have developed a hardware algorithm for generating powers of an operand, such as recirocal, square root, reciprocal square root, reciprocal square, and so on, using a multiplier with operand modifier.4. We have developed a hardware algorithm for addition under the assumption of left-to-righ input arrival, which is optimal in theory and very efficient in practice.5. We have developed a hardware algorithms for modular division with very large modulus which is required in cryptosystems. It is based on the binay GCD algorithm.6. We have developed a hardware algorithms for division in GF (2^m) which is required in coding and cryptosystems, and designed and implemented an LSI based on it. We have also developed a fast algorithms for multiplicative inversion in GF (2^m) based Fermar's theorem.7. We have developed a fast addition algorithm on an elliptic curve over GF (2^n) using the projective coordinates which is required in public-key cryptosystems.8. We have shown that the VLSI layout problem of a bit slice of an adder tree can be treated as the minimum cut linear arrangement problem of its corresponding p-q dag, and proposed two algorithms for minimum cut linear arrangement of p-q dags.

1. 针对三维计算机图形学中经常出现的三维矢量欧几里得范数问题，提出了一种计算三维矢量欧几里得范数的硬件算法，并在此基础上设计并实现了一个大规模集成电路。我们开发了一种出现在计算机图形学中的立方体生根的硬件算法，并在此基础上设计并实现了一个大规模集成电路。我们开发了一种硬件算法，用于使用带操作数修饰符的乘法器生成操作数的幂，如倒数、平方根、倒数平方根、倒数平方等。我们开发了一种假设从左到右输入到达的加法硬件算法，该算法在理论上是最优的，在实践中是非常有效的。我们开发了一种用于密码系统中具有很大模量的模除法的硬件算法。它基于二进制GCD算法。我们开发了编码和密码系统中需要的GF （2^m）除法的硬件算法，并在此基础上设计和实现了一个大规模集成电路。我们还开发了一种基于Fermar定理的GF （2^m）乘法反演的快速算法。我们在GF （2^n）上的椭圆曲线上，利用公钥密码系统中需要的射影坐标，开发了一种快速加法算法。我们证明了加法树位片的VLSI布局问题可视为其对应的p-q段的最小切割线性排列问题，并提出了两种p-q段的最小切割线性排列算法。