Research on synthesis of easily-testable arithmetic circuits

我们开发了一种进位选择加法器，它可以用一个基数与操作数大小无关的测试集来测试，以及一个并行前缀加法器，它可以用一个基数与电路深度成比例的测试集来测试。对于乘法器的设计，我们开发了一个4-2加法器树，以及其他的加法器树，可以用一个基数与操作数大小无关的测试集来测试，并且还证明了任何由进位加法器组成的部分积压缩器都可以用一个基数与电路深度成正比的测试集来测试。我们还开发了一个原型工具，用于合成易于测试的并行前缀加法器和4-2加法器树。

We have developed a carry select adder which can be tested by a test set whose cardinality is independent of the operand size, and a parallel prefix adder which can be tested by a test set whose cardinality is proportional to the depth of the circuit. For multiplier design, we have developed a 4-2 adder tree, as well as other adder trees, which can be tested by a test set whose cardinality is independent of the operand size, and also shown that any partial product compressor consisting of carry save adders can be tested by a test set whose cardinality is proportional to the depth of the circuit. We have also developed a prototype tool for synthesizing easily testable parallel prefix adders and 4-2 adder trees.