Studies on combined arithmetic circuits for high-speed digital signal processing
Studies on combined arithmetic circuits for high-speed digital signal processing
批准号:
08680358
负责人:
TAKAGI Naofumi
金额:
$1.6万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (C)
财政年份:
1996
资助国家:
日本
项目状态:
已结题
起止时间:
1996 至 1997
中文摘要
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英文摘要
We have developed methods for designing combined arithmetic circuits which execute consecutive addition/subtractions and multiplications appearing in degital signal processing as one operation, and also developed high-speed computing method using these circuits. The main results are as follows :1. We have designed an add-multiply-adder which executes consecutive addition, multipli-cation and addition appearing often in degital signal processing as one operation, and shown its applications.2. We have developed a new high-speed square rooting algorithm using a multiply-adder which executes consecutive multiplication and addition as one operation.3. We have developed a new method for generating powers of an operand, such as recirocal, square root, reciprocal square root, reciprocal square, reciprocal cube and so on, using a multiplier with operand modifier.4. We have developed an adder which is optimal in theory and very efficient in practice, under the assumption of left-to-righ input arrival.5. We have developed two hardware algorithms for modular division with very large modulus which is required in cryptosystems. One is based on the extended Euclidean algorithm and the other is based on the binay GCD algorithm.6. We have developed massively parallel algorithms for executing arithmetic operations on a functional memory and have developed a method for motion vector detection using them.
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Naofumi Takagi: "O(n)-depth modular exponentiation circuit algorithm" IEEE Transactions on Computers. 46・6. 701-704 (1997)
Naofumi Takagi:“O(n) 深度模幂电路算法”IEEE Transactions on Computers 46・6 (1997)。
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Naofumi Takagi: "A hardware algorithm for modular division based on the extended Euclidean algorithm" IEICE Transactions on Information and Systems. E79-D,11. 1518-1522 (1996)
Naofumi Takagi:“基于扩展欧几里德算法的模除法的硬件算法”IEICE Transactions on Information and Systems。
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Naofumi Takagi: "Generation of reciprocal, square root, and so forth by means of a multiplier with an operand modifier" IEICE Technical Report. COMD5P97-112. (1997)
Naofumi Takagi:“通过带有操作数修饰符的乘法器生成倒数、平方根等”IEICE 技术报告。
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Naofumi Takagi: "Square Rooting by Iterative Multiply-Additions" Information Processing Letters. no.60. 267-269 (1997)
Naofumi Takagi:“迭代乘法求平方根”信息处理信件。
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Naofumi Takagi: "Generating a Power of an Operand by a Tabie Look-up and a Multiplication" Proc.13th IEEE Symp. Computer Arithmetic. 126-131 (1997)
Naofumi Takagi:“通过 Tabie 查找和乘法生成操作数的幂”Proc.13th IEEE Symp。
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共 8 条
Research on high-performance and highly-dependable floating-point arithmetic unit arrays by contriving data representation
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批准号:24300019
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项目类别:Grant-in-Aid for Scientific Research (B)
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资助金额:$6.74万
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财政年份:2012
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负责人:TAKAGI Naofumi
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依托单位:
Research on synthesis of easily-testable arithmetic circuits
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批准号:20300016
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项目类别:Grant-in-Aid for Scientific Research (B)
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资助金额:$7.4万
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财政年份:2008
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负责人:TAKAGI Naofumi
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依托单位:
Researches on hardware algorithms for arithmetic operations in finite fields.
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批准号:14380142
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项目类别:Grant-in-Aid for Scientific Research (B)
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资助金额:$9.28万
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财政年份:2002
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负责人:TAKAGI Naofumi
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依托单位:
Studies on hardware algorithms for high-performance arithmetic circuits
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批准号:10680349
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项目类别:Grant-in-Aid for Scientific Research (C)
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资助金额:$1.98万
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财政年份:1998
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负责人:TAKAGI Naofumi
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依托单位:
海外基金