Studies on combined arithmetic circuits for high-speed digital signal processing
高速数字信号处理组合运算电路的研究
基本信息
- 批准号:08680358
- 负责人:
- 金额:$ 1.6万
- 依托单位:
- 依托单位国家:日本
- 项目类别:Grant-in-Aid for Scientific Research (C)
- 财政年份:1996
- 资助国家:日本
- 起止时间:1996 至 1997
- 项目状态:已结题
- 来源:
- 关键词:
项目摘要
We have developed methods for designing combined arithmetic circuits which execute consecutive addition/subtractions and multiplications appearing in degital signal processing as one operation, and also developed high-speed computing method using these circuits. The main results are as follows :1. We have designed an add-multiply-adder which executes consecutive addition, multipli-cation and addition appearing often in degital signal processing as one operation, and shown its applications.2. We have developed a new high-speed square rooting algorithm using a multiply-adder which executes consecutive multiplication and addition as one operation.3. We have developed a new method for generating powers of an operand, such as recirocal, square root, reciprocal square root, reciprocal square, reciprocal cube and so on, using a multiplier with operand modifier.4. We have developed an adder which is optimal in theory and very efficient in practice, under the assumption of left-to-righ input arrival.5. We have developed two hardware algorithms for modular division with very large modulus which is required in cryptosystems. One is based on the extended Euclidean algorithm and the other is based on the binay GCD algorithm.6. We have developed massively parallel algorithms for executing arithmetic operations on a functional memory and have developed a method for motion vector detection using them.
我们已经开发了用于设计组合运算电路的方法,该组合运算电路将数字信号处理中出现的连续加/减和乘法作为一个操作来执行,并且还开发了使用这些电路的高速计算方法。主要研究结果如下:1.设计了一种加乘加法器,将数字信号处理中经常出现的连续的加、乘、加作为一次运算来执行,并给出了它的应用.提出了一种新的高速平方根算法,该算法采用乘加器,将连续的乘加运算作为一次运算来执行.提出了一种利用带操作数修饰符的乘法器生成操作数的幂的新方法,如倒数、平方根、倒数平方根、倒数立方等.在输入端从左到右到达的假设下,我们设计了一个理论上最优,实际上非常有效的加法器.针对密码体制中要求的大模数模除法,我们提出了两种硬件算法。一种是基于扩展的欧几里德算法,另一种是基于binay GCD算法.我们已经开发了大规模的并行算法执行算术运算的功能存储器,并开发了一种方法,使用它们的运动矢量检测。
项目成果
期刊论文数量(0)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
Naofumi Takagi: "O(n)-depth modular exponentiation circuit algorithm" IEEE Transactions on Computers. 46・6. 701-704 (1997)
Naofumi Takagi:“O(n) 深度模幂电路算法”IEEE Transactions on Computers 46・6 (1997)。
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- 影响因子:0
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Naofumi Takagi: "A hardware algorithm for modular division based on the extended Euclidean algorithm" IEICE Transactions on Information and Systems. E79-D,11. 1518-1522 (1996)
Naofumi Takagi:“基于扩展欧几里德算法的模除法的硬件算法”IEICE Transactions on Information and Systems。
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- 影响因子:0
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Naofumi Takagi: "Generation of reciprocal, square root, and so forth by means of a multiplier with an operand modifier" IEICE Technical Report. COMD5P97-112. (1997)
Naofumi Takagi:“通过带有操作数修饰符的乘法器生成倒数、平方根等”IEICE 技术报告。
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- 影响因子:0
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Naofumi Takagi: "Square Rooting by Iterative Multiply-Additions" Information Processing Letters. no.60. 267-269 (1997)
Naofumi Takagi:“迭代乘法求平方根”信息处理信件。
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- 影响因子:0
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Naofumi Takagi: "Generating a Power of an Operand by a Tabie Look-up and a Multiplication" Proc.13th IEEE Symp. Computer Arithmetic. 126-131 (1997)
Naofumi Takagi:“通过 Tabie 查找和乘法生成操作数的幂”Proc.13th IEEE Symp。
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TAKAGI Naofumi其他文献
TAKAGI Naofumi的其他文献
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{{ truncateString('TAKAGI Naofumi', 18)}}的其他基金
Research on high-performance and highly-dependable floating-point arithmetic unit arrays by contriving data representation
基于数据表示设计的高性能高可靠浮点运算单元阵列研究
- 批准号:
24300019 - 财政年份:2012
- 资助金额:
$ 1.6万 - 项目类别:
Grant-in-Aid for Scientific Research (B)
Research on synthesis of easily-testable arithmetic circuits
易测试运算电路的综合研究
- 批准号:
20300016 - 财政年份:2008
- 资助金额:
$ 1.6万 - 项目类别:
Grant-in-Aid for Scientific Research (B)
Researches on hardware algorithms for arithmetic operations in finite fields.
研究有限域算术运算的硬件算法。
- 批准号:
14380142 - 财政年份:2002
- 资助金额:
$ 1.6万 - 项目类别:
Grant-in-Aid for Scientific Research (B)
Studies on hardware algorithms for high-performance arithmetic circuits
高性能运算电路的硬件算法研究
- 批准号:
10680349 - 财政年份:1998
- 资助金额:
$ 1.6万 - 项目类别:
Grant-in-Aid for Scientific Research (C)
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