Study on Design Methodologies for Scalable System-LSI Architectures

本研究项目的目标是开发可扩展系统lsi架构的设计方法。本项目的研究成果如下：(1)可扩展系统- lsi仿真器的开发：本项目开发了一个仿真器，该仿真器由一个基于CPCI的PC卡和两个安装fpga的CPCI卡组成，使设计人员能够快速探索系统- lsi的大设计空间。(2)可扩展系统lsi的架构开发和设计空间；该项目已经开发了一些适合可扩展系统lsi的技术，例如(i) PPRAM（并行处理RAM）架构（lsi内部通信接口，动态可变行大小缓存等），（ii）可变数据路径/内存路径宽度的优化技术，（iii）减轻对CMP（芯片多处理器）的数据/控制依赖的技术，（iv） lsi内部信号技术减少串扰的影响。(3) CAD工具的开发：本项目开发了多个CAD工具，如(i)用于检测程序热点的实时在线分析器，（ii）用于软核处理器和Valen-C程序的硬件/软件协同设计环境。(4)高性能/低功耗微处理器架构的开发和评估；该项目已经开发了一些适用于高性能/低功耗微处理器的技术，例如(i)利用具有不同性能/功耗特性的多个功能模块的动态模块选择技术，（ii）动态电压缩放处理器的实时任务调度算法，（iii）功耗感知内存层次结构，（iv）将CCC（通用情况计算）原则应用于内存参考行为的缓存内存架构。(5)可扩展系统lsi应用的开发：该项目开发了一些可扩展系统lsi应用，包括(i) RSA密码处理器，（ii） MPEG2 AAC解码器，（iii）计算化学程序中用于ERI（电子排斥积分）计算的专用处理器。少

The objective of this research project is to develop design methodologies for scalable system-LSI architectures. The project has performed the following research results.(1) Development of scalable system-LSI emulator : The project has developed an emulator, which consists of a CPCI-based PC card and two FPGA-mounted CPCI cards, for enabling designers to explore large design space of system-LSI quickly.(2) Development of architectures for scalable system-LSI and the design space : The project has developed a couple of technologies good for scalable system-LSI, such as (i) PPRAM (Parallel Processing RAM) architectures (inter-LSI communication interface, dynamically variable line-size cache, and so on), (ii) optimizing techniques for variable datapath/memorypath width, (iii) techniques for alleviating data/control dependences on CMP (chip multiprocessor), (iv) intra-LSI signaling technique reducing the effect of crosstalk.(3) Development of CAD tools : The project has developed a couple … More of CAD tools, such as (i) realtime online profiler for detecting program hot-spots, (ii) hardware/software codesign environment for soft-core processor and Valen-C programs.(4) Development and evaluation of high-performance/low-power microprocessor architectures : The project has developed a couple of technologies good for high-performance/low-power microprocessors, such as (i) dynamic module selection technique utilizing multiple functional modules with different performance/power properties, (ii) realtime task scheduling algorithm for DVS (dynamic voltage scaling) processors, (iii) power-aware memory hierarchy, (iv) cache memory architectures adapting CCC (common case computation) principle to memory reference behavior.(5) Development of applications of scalable system-LSI : The project has developed some scalable system-LSI applications, including (i) RSA cipher processor, (ii) MPEG2 AAC decoder, (iii) special-purpose processor for ERI (electron repulsion integral) calculations in computational chemistry programs. Less