Study on Design Methodologies for Scalable System-LSI Architectures

可扩展系统LSI架构的设计方法研究

• 批准号: 11308011
• 负责人: MURAKAMI Kazuaki
• 金额: $ 19.65万
• 依托单位: Kyushu University
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (A).
• 财政年份: 1999
• 资助国家: 日本
• 起止时间: 1999 至 2000
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-11308011/
• 关键词: system LSI; emulation; design optimization; FPGA; low power design; computer architecture; HW; SW codesign; dynamic optimization; 分散演算

The objective of this research project is to develop design methodologies for scalable system-LSI architectures. The project has performed the following research results.(1) Development of scalable system-LSI emulator : The project has developed an emulator, which consists of a CPCI-based PC card and two FPGA-mounted CPCI cards, for enabling designers to explore large design space of system-LSI quickly.(2) Development of architectures for scalable system-LSI and the design space : The project has developed a couple of technologies good for scalable system-LSI, such as (i) PPRAM (Parallel Processing RAM) architectures (inter-LSI communication interface, dynamically variable line-size cache, and so on), (ii) optimizing techniques for variable datapath/memorypath width, (iii) techniques for alleviating data/control dependences on CMP (chip multiprocessor), (iv) intra-LSI signaling technique reducing the effect of crosstalk.(3) Development of CAD tools : The project has developed a couple … More of CAD tools, such as (i) realtime online profiler for detecting program hot-spots, (ii) hardware/software codesign environment for soft-core processor and Valen-C programs.(4) Development and evaluation of high-performance/low-power microprocessor architectures : The project has developed a couple of technologies good for high-performance/low-power microprocessors, such as (i) dynamic module selection technique utilizing multiple functional modules with different performance/power properties, (ii) realtime task scheduling algorithm for DVS (dynamic voltage scaling) processors, (iii) power-aware memory hierarchy, (iv) cache memory architectures adapting CCC (common case computation) principle to memory reference behavior.(5) Development of applications of scalable system-LSI : The project has developed some scalable system-LSI applications, including (i) RSA cipher processor, (ii) MPEG2 AAC decoder, (iii) special-purpose processor for ERI (electron repulsion integral) calculations in computational chemistry programs. Less

本研究计画的目标是发展可扩充系统大规模积体电路架构的设计方法。本项目取得了以下研究成果。(1)可扩展系统LSI仿真器的开发：该项目开发了一个仿真器，它由一个基于CPCI的PC卡和两个FPGA安装的CPCI卡组成，使设计人员能够快速探索系统LSI的大设计空间。(2)可扩展系统LSI架构的开发和设计空间：该项目开发了几种适用于可扩展系统LSI的技术，如（i）PPRAM（并行处理RAM）体系结构（LSI间通信接口、动态可变行大小高速缓存等），（ii）用于可变数据路径/存储器路径宽度的优化技术，（iii）用于减轻对CMP（芯片多处理器）的数据/控制依赖性的技术，（iv）减少串扰影响的LSI内信令技术。(3)开发CAD工具：该项目开发了几个 ...更多信息 CAD工具，如（i）用于检测程序热点的实时在线分析器，（ii）用于软核处理器和Valen-C程序的硬件/软件协同设计环境。(4)高性能/低功耗微处理器架构的开发和评估：该项目开发了一系列适用于高性能/低功耗微处理器的技术，如（i）利用多个具有不同性能/功耗特性的功能模块的动态模块选择技术，（ii）DVS的实时任务调度算法（动态电压缩放）处理器，（iii）功率感知存储器层级，（iv）使CCC（公共情况计算）原理适应于存储器引用行为的高速缓存存储器架构。(5)开发可扩展系统-LSI的应用：该项目开发了一些可扩展系统-LSI应用，包括（i）RSA密码处理器，（ii）MPEG 2 AAC解码器，（iii）计算化学程序中ERI（电子排斥积分）计算的专用处理器。少

项目成果

H.Yamashita et al.: "Variable Size Analysis and Validation of Computation Quality"Proc.of Workshop on High-Level Design Validation and Test (HLDVT'00). 95-100 (2000)

H.Yamashita 等人：“可变尺寸分析和计算质量验证”Proc.of Workshop on High-Level Design Validation and Test (HLDVT00)。

T,Ishihara et al.: "A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors"Proc,of Design Automation and Test in Europe (DATE2000). (印刷中). (2000)

T,Ishihara 等人：“针对特定应用嵌入式处理器的目标代码合并的功耗降低技术”Proc,of Design Automation and Test in Europe (DATE2000)（出版中）。

Inoue, K., Ishihara, T., and Murakami, K.: "Way-Predicting Set-Associative Cache for high Performance and Low Energy Consumption"Proc. of International Symposium on Low Power Electronics and Design (ISLPED'99). (1999)

Inoue, K.、Ishihara, T. 和 Murakami, K.：“用于高性能和低能耗的路预测集关联缓存”Proc。

H.Yasuura et al.: "System LSI Design Methods for Low Power LSIs"IEICE Transactions on Electronics. E83-C・2. 143-152 (2000)

H.Yasuura 等人：“低功耗 LSI 的系统 LSI 设计方法”IEICE Transactions on Electronics。143-152 (2000)。

Murakami, K.: "Invited Talk : Current Status of PPRAM"Proc. 6th International Conference on VLSI and CAD (ICVE'99). 266-276 (1999)

Murakami, K.：“邀请演讲：PPRAM 的现状”Proc。