Development of Architectures and Design Methodologies of Customizable IP Cores for System-LSI's

本课题的研究目标是为系统级大规模集成电路开发可定制IP核的体系结构和设计方法。该项目取得了以下研究成果：(1)可定制IP核体系结构的开发：开发了几种可定制的处理器和协处理器作为可定制IP核，并给出了这些IP核的设计方法。开发的技术包括(I)可定制处理器，其功能单元的性能和能量消耗可以在编译时或运行时(重新)配置和优化，(Ii)可定制协处理器，其功能和组织可以在运行时重新配置，(Iii)在线硬件综合技术，为可定制协处理器产生硬件配置信息，等等。(2)可定制存储核心架构的开发：该项目已经开发了几个可定制存储核心和相关技术；(I)基于对指令位模式出现频率的统计分析，为目标程序定制指令译码，以便从程序只读存储器中取出指令所消耗的功率；(Ii)基于取出指令地址的概况，定制和减少指令高速缓冲存储器的标签查找次数，以便检查指令高速缓冲存储器标签的功耗等等。(3)开发可变大小数据路径和存储器路径的定制技术：本项目开发了一些用于分析源程序中变量的动态范围的技术，然后确定数据路径和存储路径的大小，以达到性能和功耗之间的折衷。

The objective of this research project is to develop architectures and design methodologies of customizable IP cores for system-LSI's. The project has performed the following research results.(1) Development of customizable IP core architectures : The project has developed several customizable processors and co-processors as customizable IP cores, and design methodologies for these IP cores. The technologies developed include (I) customizable processors where the performance and energy consumption of their functional units can be (re)configured and optimized at either compile time or run time, (ii)customizable co-processors whose functionality and organization can be reconfigured at run time, (iii) online hardware synthesis technology which produces hardware configuration information for the customizable co-processors, and so on.(2) Development of customizable memory core architectures : The project has developed several customizable memory cores and related technologies ; (I) customizing the instruction decoding for object programs, based on the statistical analysis on the appearance frequency of bit patterns of instructions, so that the power consumed for fetching instructions from a program ROM, (ii) customizing and reducing the number of tag lookups for instruction cache, based on the profile of instruction fetch addresses, so that the power consumed for checking the instruction cache tags, and so on.(3) Development of customization techniques for variable-size datapath and memory-path : The project has developed some techniques for analyzing the dynamic ranges of variables in source programs, and then determining the size of datapath and memory-path so that tradeoff between the performance and power consumption can be achieved.