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Development of System-LSI Architectures Based on Merged Memory/Logic Technology

基于合并存储器/逻辑技术的系统LSI架构的开发

基本信息

批准号：
09358005
负责人：
MURAKAMI Kazuaki
金额：
$ 18.3万
依托单位：
KYUSHU UNIVERSITY
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (A)
财政年份：
1997
资助国家：
日本
起止时间：
1997 至 1999
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-09358005/
关键词：
merged memory logic system LSI parallel distributed processing inter-LSI interconnect low power circuit computer architecture cache memory computational science メモリ・ロジック混載並列・分散処理性能評価大規模集積回路

项目摘要

The objectives of this research project are to develop system-LSI architectures and computer-system architectures, or PPRAM (Parallel Processing RAM), which are based mainly on merged memory/logic technology, parallel/distributed processing technology , and inter-LSI high-speed interconnect technology. The project has performed the following research results.(1) Inter-LSI high-speed interconnect standard, or PPRAM-Link : The project has defined a set of specifications for physical layer, logical layer, and API of PPRAM-Link ; and then it has implemented these specifications in several ways.(2) Reference PPRAM architectures : The project has developed a couple of architectures good for merged DRAM/logic system-LSI, such as (I) shared-register CMP (chip multiprocessor), (ii) statically/dynamically variable line-size cache, (iii) way-predicting set-associative cache.(3) DRAM refresh architectures for merged DRAM/logic LSI : The project has developed a couple of architectures good for merg … More ed DRAM/logic system-LSI so that alleviate the DRAM refresh characteristics to be worsened by on-chip logic.(4) Hardware/software codesign methodology for embedded system-LSI : The project has developed a hardware/software codesign methodology based on soft-core processor and Valen-C technologies.(5) Software-controlled low power architectures : The project has designed a processor architecture, or PowerPro, which can optimize the power consumption by means of software control according to the system load.(6) Test methodology for system-LSI : The project has proposed a test methodology good for system-LSI, which combines BIST and external test.(7) PPRAM-based MOE (molecular orbital calculation engine) : The project has developed some PPRAM applications, including MOE chips and MOE system. The MOE chip consists of a 32-bit integer RISC processor, a 76-bit MO-specific floating-point processor, 1Mb SRAM, and a PPRAM-Link interface. The MOE system consists of a number of MOE boards, each of which includes five MOE chips and a bridge chip for PPRAM-Link and IEEE1394.(8) PPRAM-based realtime digital-watermarking engine for movies : Another PPRAM application is a realtime digital-watermarking engine for movies. The project has implemented a suite of wavelet transformation function, PPRAM-Link interface and PCI-bus interface by means of FPGA. Less

本研究项目的目标是开发系统LSI架构和计算机系统架构，即PPRAM（并行处理RAM），其主要基于合并存储器/逻辑技术、并行/分布式处理技术以及LSI间高速互连技术。项目取得了以下研究成果：(1)LSI间高速互连标准，即PPRAM-Link：该项目定义了一套PPRAM-Link物理层、逻辑层和API的规范； (2) 参考 PPRAM 架构：该项目开发了几种适合合并 DRAM/逻辑系统 LSI 的架构，例如 (I) 共享寄存器 CMP（芯片多处理器）、(ii) 静态/动态可变行大小缓存、(iii) 方式预测集关联缓存。(3) 用于合并的 DRAM 刷新架构 DRAM/逻辑LSI：该项目开发了几种有利于合并DRAM/逻辑系统LSI的架构，从而减轻片上逻辑导致的DRAM刷新特性恶化。(4)嵌入式系统LSI的硬件/软件协同设计方法：该项目开发了一种基于软核处理器和Valen-C技术的硬件/软件协同设计方法。(5) 软件控制的低功耗架构：该项目设计了一种处理器架构，即PowerPro，可以根据系统负载通过软件控制来优化功耗。（6）系统LSI的测试方法：该项目提出了一种适合系统LSI的测试方法，将BIST和外部测试相结合。（7）基于PPRAM的MOE（分子轨道计算引擎）：该项目开发了一些PPRAM应用，包括MOE 芯片和MOE系统。 MOE芯片由32位整数RISC处理器、76位MO专用浮点处理器、1Mb SRAM和PPRAM-Link接口组成。 MOE系统由多个MOE板组成，每个MOE板包括五个MOE芯片和一个用于PPRAM-Link和IEEE1394的桥接芯片。 (8)基于PPRAM的电影实时数字水印引擎：另一个PPRAM应用是电影实时数字水印引擎。该项目通过FPGA实现了一套小波变换功能、PPRAM-Link接口和PCI总线接口。较少的