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Development of System-LSI Architectures Based on Merged Memory/Logic Technology

Development of System-LSI Architectures Based on Merged Memory/Logic Technology
基于合并存储器/逻辑技术的系统LSI架构的开发
批准号:
09358005
负责人:
MURAKAMI Kazuaki
金额:
$18.3万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (A)
财政年份:
1997
资助国家:
日本
项目状态:
已结题
起止时间:
1997 至 1999

项目摘要

项目成果

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中文摘要
翻译
这项研究项目的目标是开发系统-LSI体系结构和计算机系统体系结构,或PPRAM(并行处理RAM),主要基于合并的存储器/逻辑技术、并行/分布式处理技术和LSI间高速互连技术。(1)LSI间高速互连标准PPRAM-Link:定义了一套PPRAM-Link的物理层、逻辑层和API规范;(2)参考…体系结构:本项目开发了几种适合于合并动态随机存取存储器/逻辑系统大规模集成电路的体系结构,例如(I)共享寄存器多处理器(芯片多处理器),(Ii)静态/动态可变行长高速缓存,(Iii)路预测组关联高速缓存。(3)用于合并动态随机存取存储器/逻辑大规模集成电路的动态随机存取存储器刷新体系结构:本项目开发了几种适合合并大规模集成电路的体系结构更多的DRAM/逻辑系统-LSI,以缓解片上逻辑导致的DRAM刷新特性的恶化。(4)嵌入式系统-LSI的软硬件协同设计方法:本项目开发了一种基于软核处理器和Valen-C技术的软硬件协同设计方法。(5)软件控制的低功耗体系结构:本项目设计了一种处理器体系结构,即PowerPro,它可以根据系统负载通过软件控制的方式来优化功耗。(6)系统-LSI的测试方法:本项目提出了一种适合于系统-LSI的测试方法,基于PPRAM的MOE(分子轨道计算引擎):该项目已经开发了一些PPRAM应用,包括MOE芯片和MOE系统。MOE芯片由32位整数RISC处理器、76位MO专用浮点处理器、1Mb SRAM和PPRAM-Link接口组成。MOE系统由多个MOE板组成,每个MOE板包括五个MOE芯片和一个用于PPRAM-Link和IEEE1394的桥接芯片。(8)基于PPRAM的电影实时数字水印引擎:另一个PPRAM应用是电影的实时数字水印引擎。该项目利用现场可编程门阵列实现了一套小波变换功能、PPRAM-Link接口和PCI-Bus接口。较少
英文摘要
The objectives of this research project are to develop system-LSI architectures and computer-system architectures, or PPRAM (Parallel Processing RAM), which are based mainly on merged memory/logic technology, parallel/distributed processing technology , and inter-LSI high-speed interconnect technology. The project has performed the following research results.(1) Inter-LSI high-speed interconnect standard, or PPRAM-Link : The project has defined a set of specifications for physical layer, logical layer, and API of PPRAM-Link ; and then it has implemented these specifications in several ways.(2) Reference PPRAM architectures : The project has developed a couple of architectures good for merged DRAM/logic system-LSI, such as (I) shared-register CMP (chip multiprocessor), (ii) statically/dynamically variable line-size cache, (iii) way-predicting set-associative cache.(3) DRAM refresh architectures for merged DRAM/logic LSI : The project has developed a couple of architectures good for merg … More ed DRAM/logic system-LSI so that alleviate the DRAM refresh characteristics to be worsened by on-chip logic.(4) Hardware/software codesign methodology for embedded system-LSI : The project has developed a hardware/software codesign methodology based on soft-core processor and Valen-C technologies.(5) Software-controlled low power architectures : The project has designed a processor architecture, or PowerPro, which can optimize the power consumption by means of software control according to the system load.(6) Test methodology for system-LSI : The project has proposed a test methodology good for system-LSI, which combines BIST and external test.(7) PPRAM-based MOE (molecular orbital calculation engine) : The project has developed some PPRAM applications, including MOE chips and MOE system. The MOE chip consists of a 32-bit integer RISC processor, a 76-bit MO-specific floating-point processor, 1Mb SRAM, and a PPRAM-Link interface. The MOE system consists of a number of MOE boards, each of which includes five MOE chips and a bridge chip for PPRAM-Link and IEEE1394.(8) PPRAM-based realtime digital-watermarking engine for movies : Another PPRAM application is a realtime digital-watermarking engine for movies. The project has implemented a suite of wavelet transformation function, PPRAM-Link interface and PCI-bus interface by means of FPGA. Less
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通讯作者:
Kai, K., Inoue, A., Ohsawa, T., and Murakami, K.: "Analyzing and Reducing the Impact of Shorter Data Retention Time on the Performance of Merged DRAM/Logic LSIs"IEICE Trans. on Electronics. E81-C, 9. 1448-1454 (1998)
Kai, K.、Inoue, A.、Ohsawa, T. 和 Murakami, K.:“分析并减少较短数据保留时间对合并 DRAM/逻辑 LSI 性能的影响”IEICE Trans。
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通讯作者:
Inoue, K., Kai, K., and Murakami, K.: "Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs"Proceedings of the Fifth International Symposium on High-Performance Computer Architecture (HPCA-5). 218-222 (19
Inoue, K.、Kai, K. 和 Murakami, K.:“利用合并 DRAM/逻辑 LSI 的高片上存储器带宽的动态可变行大小高速缓存”第五届高性能计算机体系结构国际研讨会论文集(
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通讯作者:
K.Inoue et al.: "High Bandwidth,Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs" IEICE Trans.on Electronics. E81-C・9. 1438-1447 (1998)
K. Inoue 等人:“用于合并 DRAM/逻辑 LSI 的高带宽、可变线大小缓存架构”IEICE Trans.on Electronics。1438-1447。
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15
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