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Study of Interface Control in Ultra-thin High-k Film on Silicon Substrate

硅基超薄高介电常数薄膜的界面控制研究

基本信息

批准号：
13852009
负责人：
TORIUMI Akira
金额：
$ 76.29万
依托单位：
The University of Tokyo
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (S)
财政年份：
2001
资助国家：
日本
起止时间：
2001 至 2005
项目状态：
已结题

项目摘要

This research target was to scientifically judge the possibility of usability of ultra-thin high-k dielectric films for next generation CMOS ULSI. Main results obtained are described below.1.Understanding of origin of high dielectric constants of high-k materials proposed and constructing a guiding principle of high-k materials design.(1)Phonon modes of high-k materials have been clearly provided using far-infrared absorption analysis.(2)Y or Si doping into HfO2 can enhance the dielectric constant (〜30) through the phase transformation.(3)La doping can enhance crystallization temperature as well as dielectric constant.(4)The dielectric constants were quantitatively analyzed through both molar volume change and molar polarizability and a guiding principle for designing high-k dielectrics was proposed.2.Understanding and control of high-k/Si interface layer(1)The interface layer growth at HfO2/Si was modeled as parameters of substrate orientation, oxidation time, and temperature. This fact has clarified that high-k/Si interface layer growth mechanism is significantly different from Si surface oxidation.(2)By taking account of atomic oxygen as oxidation species the interface layer growth model was quantitatively constructed and a guiding principle for the interface layer control was proposed.Based upon those results, we challenged to demonstrate sub-nm EOT high-k oxides. Though still some optimization was needed for the interface characteristics improvement, we have achieved high-k gate stack with EOT=0.8 nm and 5 orders smaller leakage current compared to SiO2 case. Thus, the numerical target of this research has been fully achieved.Furthermore, high-k dielectrics on Ge were also partly studied and new features of this system, particularly in the interface layer, have been observed. This result provides us a new research target for the next generation ULSI devices.

本研究的目的是科学判断超薄高介电常数薄膜应用于下一代CMOS ULSI的可能性。主要研究结果如下：1.提出了对高介电常数材料高介电常数成因的认识，构建了高介电常数材料设计的指导原则。（1）利用远红外吸收分析方法，清晰地给出了高k材料的声子模。(2)Y或Si掺杂到HfO 2中可以通过相变提高介电常数（ε 30）。(3)La掺杂可以提高结晶温度以及介电常数。（4）从摩尔体积变化和摩尔极化率两个方面定量分析了HfO 2/Si界面层的介电常数，并提出了设计高介电常数介电层的指导原则。2.高介电常数/Si界面层的理解和控制（1）将HfO 2/Si界面层的生长模型化为衬底取向、氧化时间和温度等参数。这一事实阐明了高k/Si界面层的生长机制与Si表面氧化有显著不同。(2)By以原子氧为氧化物种，定量地建立了界面层生长模型，提出了界面层控制的指导原则，并以此为基础，对亚纳米EOT高k氧化物进行了研究。虽然仍然需要一些优化的界面特性的改善，我们已经实现了高k栅堆叠EOT=0.8 nm和5个订单相比，SiO2的情况下，更小的漏电流。此外，我们还对高介电常数的锗离子进行了部分研究，观察到了该系统的一些新的特征，特别是在界面层中。这一结果为下一代超大规模集成电路器件提供了新的研究方向。

项目成果

期刊论文数量（108）

专著数量（0）

科研奖励数量（0）

会议论文数量（0）

专利数量（0）

Permittivity Enhancement of Hf_<(1-x)>Si_xO_2 Film with High Temperature Annealing

高温退火增强Hf_<(1-x)>Si_xO_2薄膜的介电常数

DOI：
发表时间：
2005
期刊：
Ext.Abst. 2005 Int.Conf. on Solid State Devices and Materials (SSDM)
影响因子：
0
作者：
K.Tomida;K.Kita;A.Toriumi
通讯作者：
A.Toriumi

Difference between O_2 and N_2 Annealing Effects on CVD-SiO_2 Film Quality Studied by Open-Circuit Measurement

开路测量研究O_2和N_2退火对CVD-SiO_2薄膜质量影响的差异

DOI：
发表时间：
2004
期刊：
Extended Abstracts of 2004 International Conference on Solid State Devices and Materials 2004
影响因子：
0
作者：
A.Toriumi;A.V.Baranov;K.Kita et al.;池沢道男;M.Toyama et al.;A.V.Baranov;K.Tomida et al.;K.Kyuno et al.;A.V.Fedorov;H.Shimizu et al.;Y.Masumoto;J.Qi;Y.Masumoto;Y.Masumoto;Y.Masumoto;A.V.Fedorov;K.kita et al.
通讯作者：
K.kita et al.

Materials Engineering for High-k Gate Stack Technology

高 k 栅极堆叠技术的材料工程