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The Via-Programmable LSI Design Architecture using EB direct writing and it's application to Unique LSI for the Authentication device.

采用EB直写的Via可编程LSI设计架构及其在认证器件的Unique LSI中的应用。

基本信息

批准号：
18560355
负责人：
FUJINO Takeshi
金额：
$ 2.48万
依托单位：
Ritsumeikan University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (C)
财政年份：
2006
资助国家：
日本
起止时间：
2006 至 2007
项目状态：
已结题

项目摘要

Integrated electronic system composed of microprocessors and large memories can be realized as a single chip owing to the progress of micro-fabrication technology of VLSI. The photo-mask cost of standard-cell-based ASICs has been increased so prohibitively that low-volume production LSIs are difficult to fabricate due to high non-recurring engineering (NRE) cost including mask cost. Electron Beam direct writing (EBDW) technology is the most cost-effective lithography tool, because it is mask-less technology. The EB exposure time will be greatly reduced by applying character-projection (CP) EB direct writing. So we have developed new LSI device architecture appropriate for this CP EB direct-writing.In 2006, we proposed the user-programmable architecture called VPEX (Via Programmable logic device using EXclusive-or array), in which the hardware logic can be programmed by changing layout patterns on 2 via-layers. The logic element (LE) of VPEX consists of complex-gate-type EXclusive OR (EXOR) and Inverter (NOT) gates. The single LE can output 12 logics which include NOT, Buffer (BUF), all 2-inputs logic functions, 3-inputs AOI21 and inverted-output multiplexer (MUXI) by changing via-1 layout pattern. Furthermore, via-1 layout is optimized for CP EB direct writing.In 2007, we compared the performance of area, speed, and power consumption of VPEX with that of standard-cell-based ASICs and FPGAs. As a result, the speed performance of VPEX was much better than FPGAs and about 1.3-1.6 times worse than standard-cells. Furthermore we developed LSI test chip which applying VPEX architecture. The process technology used in this chip is 0.18 urn CMOS. We will evaluate this chip in the near future.

随着超大规模集成电路微细加工技术的发展，由微处理器和大容量存储器组成的集成电子系统可以在单片上实现。基于标准单元的ASIC的光掩模成本已经增加得如此之高，以至于由于包括掩模成本在内的高非重复工程（NRE）成本，难以制造小批量生产LSI。电子束直写（EBDW）技术是最具成本效益的光刻工具，因为它是无掩模技术。采用字符投影（CP）电子束直写，可大大缩短电子束曝光时间。2006年，我们提出了用户可编程架构VPEX（Via Programmable logic device using EXCLUSIVE-OR array），通过改变2个通孔层上的布局图案，可以对硬件逻辑进行编程。VPEX的逻辑元件（LE）由复合门型异或（EXOR）和反相（NOT）门组成。通过改变通孔1的布局模式，单个LE可以输出12个逻辑，包括NOT、缓冲器（BUF）、所有2输入逻辑功能、3输入AOI 21和反相输出多路复用器（MUXI）。2007年，我们将VPEX的面积、速度和功耗性能与基于标准单元的ASIC和FPGA进行了比较。因此，VPEX的速度性能比FPGA好得多，比标准单元差约1.3-1.6倍。在此基础上，开发了采用VPEX体系结构的大规模集成电路测试芯片.该芯片采用0.18 μ mCMOS工艺。我们将在不久的将来评估这款芯片。