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The Via-Programmable LSI Design Architecture using EB direct writing and it's application to Unique LSI for the Authentication device.

The Via-Programmable LSI Design Architecture using EB direct writing and it's application to Unique LSI for the Authentication device.
采用EB直写的Via可编程LSI设计架构及其在认证器件的Unique LSI中的应用。
批准号:
18560355
负责人:
FUJINO Takeshi
金额:
$2.48万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (C)
财政年份:
2006
资助国家:
日本
项目状态:
已结题
起止时间:
2006 至 2007

项目摘要

项目成果

FUJINO Takeshi的其他基金

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中文摘要
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英文摘要
Integrated electronic system composed of microprocessors and large memories can be realized as a single chip owing to the progress of micro-fabrication technology of VLSI. The photo-mask cost of standard-cell-based ASICs has been increased so prohibitively that low-volume production LSIs are difficult to fabricate due to high non-recurring engineering (NRE) cost including mask cost. Electron Beam direct writing (EBDW) technology is the most cost-effective lithography tool, because it is mask-less technology. The EB exposure time will be greatly reduced by applying character-projection (CP) EB direct writing. So we have developed new LSI device architecture appropriate for this CP EB direct-writing.In 2006, we proposed the user-programmable architecture called VPEX (Via Programmable logic device using EXclusive-or array), in which the hardware logic can be programmed by changing layout patterns on 2 via-layers. The logic element (LE) of VPEX consists of complex-gate-type EXclusive OR (EXOR) and Inverter (NOT) gates. The single LE can output 12 logics which include NOT, Buffer (BUF), all 2-inputs logic functions, 3-inputs AOI21 and inverted-output multiplexer (MUXI) by changing via-1 layout pattern. Furthermore, via-1 layout is optimized for CP EB direct writing.In 2007, we compared the performance of area, speed, and power consumption of VPEX with that of standard-cell-based ASICs and FPGAs. As a result, the speed performance of VPEX was much better than FPGAs and about 1.3-1.6 times worse than standard-cells. Furthermore we developed LSI test chip which applying VPEX architecture. The process technology used in this chip is 0.18 urn CMOS. We will evaluate this chip in the near future.
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DOI: --
发表时间: 2007
期刊:
影响因子: --
作者: [木村 峻, 松本 光崇, 泉 知論, 藤野 毅, 中野 裕文, 岩男 剛宜, 奥野 義弘, 有本 和民]
通讯作者: 有本 和民
「研究成果報告書概要(和文)」より
摘自《研究结果报告摘要(日文)》
DOI: --
发表时间: 2005
期刊:
影响因子: --
作者: [Kawauchi, et. al., Nishimura et al., Dezawa et al., Yoshizawa et al., 星野 幹雄, 星野 幹雄]
通讯作者: 星野 幹雄
DOI: --
发表时间: 2008
期刊: 電子情報通信学会技術研究報告[VIS董設計技術] VLD2007-165
影响因子: --
作者: [松本 光崇, 木村 峻, 中野 裕文, 岩男 剛宜, 奥野 義弘, 有本 和民, 泉 知論, 藤野 毅]
通讯作者: 藤野 毅
暗号回路の電力差分解析攻撃に対して耐性があるドミノ型RSL回路の提案
提出一种抵抗密码电路功率微分分析攻击的多米诺骨牌型RSL电路
DOI: --
发表时间: 2007
期刊: 電子情報通信学会技術研究報告[VLSI設計技術] VLD2007-77
影响因子: --
作者: [豊田 善靖, 木戸 健太, 下林 義明, 藤野 毅]
通讯作者: 藤野 毅
28
    Survey on water quality and benthic taxonomy at headwater of Ayeyarwady river, Myanmar
    • 批准号:
      24404004
    • 项目类别:
      Grant-in-Aid for Scientific Research (B)
    • 资助金额:
      $6.82万
    • 财政年份:
      2012
    • 负责人:
      FUJINO Takeshi
    • 依托单位:
    EVATUATION OF PRIMARY PRODUCTIVITY IN STREAM BY TWO DIMENSIONAL FLUORESCENCE MEASUREMENT METHOD
    • 批准号:
      21560533
    • 项目类别:
      Grant-in-Aid for Scientific Research (C)
    • 资助金额:
      $3.0万
    • 财政年份:
      2009
    • 负责人:
      FUJINO Takeshi
    • 依托单位:
    Via programmable logic device with tamper resistance fabricated by EB direct writing technique applied for user authentication
    • 批准号:
      20560340
    • 项目类别:
      Grant-in-Aid for Scientific Research (C)
    • 资助金额:
      $2.91万
    • 财政年份:
      2008
    • 负责人:
      FUJINO Takeshi
    • 依托单位:
    ECOLOGICAL PROCESS OF AQUATIC ECOSYSTEMS DURING IMPOUNDMENT OF A DAM
    • 批准号:
      19560509
    • 项目类别:
      Grant-in-Aid for Scientific Research (C)
    • 资助金额:
      $2.91万
    • 财政年份:
      2007
    • 负责人:
      FUJINO Takeshi
    • 依托单位: