The Via-Programmable LSI Design Architecture using EB direct writing and it's application to Unique LSI for the Authentication device.
The Via-Programmable LSI Design Architecture using EB direct writing and it's application to Unique LSI for the Authentication device.
批准号:
18560355
负责人:
FUJINO Takeshi
金额:
$2.48万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (C)
财政年份:
2006
资助国家:
日本
项目状态:
已结题
起止时间:
2006 至 2007
中文摘要
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英文摘要
Integrated electronic system composed of microprocessors and large memories can be realized as a single chip owing to the progress of micro-fabrication technology of VLSI. The photo-mask cost of standard-cell-based ASICs has been increased so prohibitively that low-volume production LSIs are difficult to fabricate due to high non-recurring engineering (NRE) cost including mask cost. Electron Beam direct writing (EBDW) technology is the most cost-effective lithography tool, because it is mask-less technology. The EB exposure time will be greatly reduced by applying character-projection (CP) EB direct writing. So we have developed new LSI device architecture appropriate for this CP EB direct-writing.In 2006, we proposed the user-programmable architecture called VPEX (Via Programmable logic device using EXclusive-or array), in which the hardware logic can be programmed by changing layout patterns on 2 via-layers. The logic element (LE) of VPEX consists of complex-gate-type EXclusive OR (EXOR) and Inverter (NOT) gates. The single LE can output 12 logics which include NOT, Buffer (BUF), all 2-inputs logic functions, 3-inputs AOI21 and inverted-output multiplexer (MUXI) by changing via-1 layout pattern. Furthermore, via-1 layout is optimized for CP EB direct writing.In 2007, we compared the performance of area, speed, and power consumption of VPEX with that of standard-cell-based ASICs and FPGAs. As a result, the speed performance of VPEX was much better than FPGAs and about 1.3-1.6 times worse than standard-cells. Furthermore we developed LSI test chip which applying VPEX architecture. The process technology used in this chip is 0.18 urn CMOS. We will evaluate this chip in the near future.
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DOI:
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[石橋 宏太, 田中 祥幸, 松本 光崇, 中野 裕文, 岩男 剛宜, 奥野 義弘, 有本 和民, 吉川 雅弥, 泉 知論, 藤野 毅]
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负责人:FUJINO Takeshi
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负责人:FUJINO Takeshi
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