Super-Low-Operating-Voltage Dependable SRAM Using Total Variability Suppression Effects in FD-SOI

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We proposed a substrate bias control scheme for an FD-SOI SRAM that suppresses inter-die variability and a 7T/14T(7-transistor/14-transistor) memory cell that can be dynamically compensate its intra-die variability. The proposed substrate bias control circuits detect inter-die threshold-voltage variation automatically, and then maximize read/write margins of memory cells to supply the substrate bias. We confirmed that a 150-nm 486-kb FD-SOI SRAM operates at 0. 42 V, in which an FS corner can be compared as much as 0. 14 V. For the 7T/14T dependable memory cell verification, we fabricated a 150-nm 576-kb FD-SOI SRAM. The 14T dependable mode allocates one bit in a 14T cell and improves its bit error rate. In our measurements, the minimum retention voltage and the minimum operating voltage were reduced by 150 mV and 320 mV in the 14T dependable mode over the 7T normal mode, respectively.