Environmental Adaptive Programmable Analog LSI

环境自适应可编程模拟LSI

• 批准号: 20500055
• 负责人: NAKATAKE SHIGETOSHI
• 金额: $ 2.91万
• 依托单位: The University of Kitakyushu
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (C)
• 财政年份: 2008
• 资助国家: 日本
• 起止时间: 2008 至 2010
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-20500055/
• 关键词: 回路とシステム; 電子デバイス; 集積回路; アナログLSI; プログラマブルLSI; FPAA; アナログ集積回路; プログラマブルアナログ回路; 基板バイアス効果; 差動増幅回路; 変動・ばらつき解析; コンパレータ回路; ADコンバータ回路

This study is focusing on the programmable technologies for analog LSIs, which serve the high tolerance to the aging degradation and environmental variation. The contributions of this study are summarized as follows;(1) We proposed the PDTB (Programmable Differential-pair Transistor Block) which make use of the differential amplifier circuit as an element, and developed the CAB (Configurable Analog Block). The CAB is composed of (a)Vth-tuning circuit by body biasing, (b)pMOS-/nMOS-PTDB, (c)pMOS/nMOS transistor array, (d)resistor and capacitor array, and (e)routing resource and switch matrix.(2) We clarified the influence on DC/AC characteristics of analog circuits by the decomposition of the channel length (L) of MOS transistors. Through evaluating the test chip, we revealed that 2-L and 4-L decomposition do not matter in the DC/AC characteristics. Furthermore, we developed the Programmable Delay Element (PDE) by applying L-decomposition with a switching mechanism.(3) We proposed the programmable metal-to-metal capacitor array which has a low temperature dependency, and also present the capacitance evaluation methodology by employing the SAR-ADC mechanism.

本研究的重点是模拟LSI的可编程技术，它对老化退化和环境变化具有很高的耐受性。本研究的主要贡献如下：（1）提出了以差分放大电路为核心的可编程差分对晶体管模块PDTB（Programmable Differential-pair Transistor Block），并开发了可配置模拟模块CAB（Configurable Analog Block）。CA B由（a）通过体偏置的Vth调谐电路、（B）pMOS-/nMOS-PTDB、（c）pMOS/nMOS晶体管阵列、（d）电阻器和电容器阵列以及（e）布线资源和开关矩阵组成。(2)本文阐明了MOS晶体管沟道长度L的分解对模拟电路DC/AC特性的影响。通过对测试芯片的评估，我们发现2-L和4-L分解对DC/AC特性没有影响。此外，我们开发了可编程延迟元件（PDE）通过应用L-分解与开关机制。(3)我们提出了一种具有低温度依赖性的可编程金属对金属电容阵列，并提出了采用SAR-ADC机制的电容评估方法。

项目成果

アナログ集積回路における容量の実現及び評価手法に関する一考察

模拟集成电路中电容的实现与评估研究

• 发表时间: 2011
• 作者: 越智敦;島津怜英;藤村徹;中武繁寿
• 通讯作者: 中武繁寿

Structured Placement with Topological Regularity Evaluation

• DOI: 10.2197/ipsjtsldm.2.222
• 发表时间: 2007-01
• 期刊: 2007 Asia and South Pacific Design Automation Conference
• 作者: S. Nakatake

STI Stress Aware Placement Optimization Based on Geometric Programming

基于几何规划的 STI 应力感知放置优化

• 发表时间: 2009
• 期刊: Proc. of ACM Great Lake Symposium on VLSI
• 作者: J.Li;B.Yang;X.Hu;Q.Dong;S.Nakatake
• 通讯作者: S.Nakatake

Regularity-oriented analog placement with diffusion sharing and well island generation

• DOI: 10.1109/aspdac.2010.5419878
• 发表时间: 2010-01
• 期刊: 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)
• 作者: S. Nakatake;M. Kawakita;Takao Ito;Masahiro Kojima;Michiko Kojima;Kenji Izumi;Tadayuki Habasaki

D-A Converter Based Variation Analysis for Analog Layout Design

基于 D-A 转换器的模拟布局设计变化分析

• 发表时间: 2010
• 期刊: Proc. of IEEE/ACM Asia South Pacific Design Automation Conference
• 作者: B. Liu;T.Fujimura;B.Yang;S.Nakatake
• 通讯作者: S.Nakatake