Estimation of Single Event Transient Pulses in Logic Cells from a Single Transistor

数字单粒子瞬态（DSET）脉冲是由离子入射在逻辑门上产生的瞬时电压扰动。由于DSET的脉宽是逻辑VLSI中软错误率的一个关键参数，因此已经通过使用专门构建的电路来广泛地测量来自逻辑单元的DSET脉宽。在这项研究中，我们首先估计数字单粒子瞬态（DSET）脉冲宽度起源于逆变器单元从高能量重离子在一个单一的n型MOSFET的瞬态电流通过使用基于表格的估计方法。结果表明，该方法适用于高能重离子辐照下DSET脉冲宽度的估计。此外，我们测量了重离子在逻辑单元中使用的p型MOSFET上的感生电流脉冲横截面，以研究横截面对逻辑单元的SET横截面的影响。根据结果，我们假设来自pMOSFET的电流脉冲引起25%的SET脉冲。

Digital Single Event Transient(DSET) pulses are momentary voltage disturbance generated at logic gates by ion incident. Since pulse-width of DSETs is a key parameter of soft error rate in the logic VLSIs, the DSET pulse-widths from a logic cell have been extensively measured by using specially built circuits. In this research, we first estimated Digital Single Event Transient(DSET) pulse-widths originated in an inverter cell from high-energy heavy-ion-induced transient current in a single n-type MOSFET by using a table-based estimation method. We showed that the estimation method is applicable to the DSET pulse-widths estimation in the case of high-energy heavy-ion irradiation. In addition, we measured heavy ion induced current pulse cross-section on the p-type MOSFET used in the logic cell, to investigate an impact of the cross-section for the SET cross-section on the logic cell. From the results, we assume that current pulses from pMOSFET induce 25% of SET pulses.