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Development of local-strain technology for crystalline Ge and its application to transistors

Development of local-strain technology for crystalline Ge and its application to transistors
晶体Ge局部应变技术的发展及其在晶体管中的应用
批准号:
23760017
负责人:
WANG Dong
金额:
$2.91万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for Young Scientists (B)
财政年份:
2011
资助国家:
日本
项目状态:
已结题
起止时间:
2011 至 2012

项目摘要

项目成果

WANG Dong的其他基金

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中文摘要
翻译
为了建立应变Ge沟道的技术,在应力源形成之后,通过拉曼光谱研究了应变对几何和热处理参数的依赖性。缺陷的产生,转化和分布也澄清了光致发光。为了制备Ge-MOSFET,提出了一种超薄SiO2/GeO 2双层Ge表面钝化方法,该方法不需要破坏真空,其界面态密度(Dit)与SiO2/Si相同。为了消除SiO2/GeO 2结构中慢陷阱的影响,提出了一种在各固定温度下优化偏压条件的深能级瞬态谱方法,对GeO 2/Ge结构进行了精确的测量。根据应变评估的结果,一个好的Ge-MOSFET的制造温度应低于500 ℃。因此,开发了一种低温工艺用于Ge-MOSFET的制造,通过该工艺,Ge晶体管的操作得到了批准。特别地,p-MOSFET的沟道迁移率比Si晶体管的沟道迁移率高四倍。
英文摘要
To establish the technology of a strained Ge channel, after stressor formation, the dependences of strain on geometric and thermal treatment parameters were investigated by Raman spectroscopy. Defect generation, transformation, and distribution were also clarified by photoluminescence. To fabricate Ge-MOSFET, an ultra-thin SiO2/GeO2bilayer Ge-surface passivation method was developed without vacuum breaking, which showed a low interface states density (Dit) in the same degree of that for SiO2/Si. To eliminate the influence of slow-traps in the SiO2/GeO2structure, a deep level transient spectroscopy method was developed with optimized bias condition at each fixed-temperature, by which an accurate Ditevaluation was performed for GeO2/Ge. According to the result of strain evaluation, a good-quality Ge-MOSFET should be fabricated at a temperature less than 500 oC. Therefore, a low-temperature process was developed for Ge-MOSFET fabrication, by which the operation of Ge transistors was approved. Particularly, the channel mobility of p-MOSFET was four times higher than that of a Si transistor.
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High Hole-Mobility Ge p-MOSFET with HfGe Schottky Source/Drain
具有 HfGe 肖特基源极/漏极的高空穴迁移率 Ge p-MOSFET
DOI: --
发表时间: 2012
期刊: Extended Abstracts of the 2012 International Conference on Solid State Devices and Materials
影响因子: --
作者: [T. Sada, K. Yamamoto, H. Yang, D. Wang, H. Nakashima]
通讯作者: H. Nakashima
Fabrication of TiN/Si Contact with Low Electron Barrier Height and Electrical Characterization of Si-On-Insulator Using Back- Gate MOSFET
低电子势垒高度的 TiN/Si 接触的制造以及使用背栅 MOSFET 的绝缘体上硅的电气特性
DOI: --
发表时间: 2012
期刊: Extended Abstracts of the 2012 International Conference on Solid State Devices and Materials
影响因子: --
作者: [K. Asakawa, K. Yamamoto, D. Wang, H. Nakashima]
通讯作者: H. Nakashima
High-quality gate-stack formation on Ge and defect termination at the interface
在 Ge 上形成高质量栅堆叠并在界面处终止缺陷
DOI: --
发表时间: 2011
期刊:
影响因子: --
作者: [H. Nakashima, K. Hirayama, K. Yamamoto, H. Yang, D. Wang]
通讯作者: D. Wang
Al/Ti/Snを用いたp形4H-SiCへのオーミックコンタクトの低温形成
使用 Al/Ti/Sn 低温形成 p 型 4H-SiC 欧姆接触
DOI: --
发表时间: 2013
期刊:
影响因子: --
作者: [畑山紘太, 山本圭介, 王冬, 中島寛]
通讯作者: 中島寛
共 32 条
    Precise strain evaluation for high-performance bipolar transistor
    • 批准号:
      21760011
    • 项目类别:
      Grant-in-Aid for Young Scientists (B)
    • 资助金额:
      $2.91万
    • 财政年份:
      2009
    • 负责人:
      WANG Dong
    • 依托单位:
    海外基金