Development of local-strain technology for crystalline Ge and its application to transistors

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To establish the technology of a strained Ge channel, after stressor formation, the dependences of strain on geometric and thermal treatment parameters were investigated by Raman spectroscopy. Defect generation, transformation, and distribution were also clarified by photoluminescence. To fabricate Ge-MOSFET, an ultra-thin SiO2/GeO2bilayer Ge-surface passivation method was developed without vacuum breaking, which showed a low interface states density (Dit) in the same degree of that for SiO2/Si. To eliminate the influence of slow-traps in the SiO2/GeO2structure, a deep level transient spectroscopy method was developed with optimized bias condition at each fixed-temperature, by which an accurate Ditevaluation was performed for GeO2/Ge. According to the result of strain evaluation, a good-quality Ge-MOSFET should be fabricated at a temperature less than 500 oC. Therefore, a low-temperature process was developed for Ge-MOSFET fabrication, by which the operation of Ge transistors was approved. Particularly, the channel mobility of p-MOSFET was four times higher than that of a Si transistor.