Development of local-strain technology for crystalline Ge and its application to transistors

晶体Ge局部应变技术的发展及其在晶体管中的应用

• 批准号: 23760017
• 负责人: WANG Dong
• 金额: $ 2.91万
• 依托单位: Kyushu University
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Young Scientists (B)
• 财政年份: 2011
• 资助国家: 日本
• 起止时间: 2011 至 2012
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-23760017/
• 关键词: 解析・評価; 半導体物性; 電子・電気材料; 先端機能デバイス; ゲルマニウム(Ge); 歪み印加; MOSFET; 高移動度チャネル; ゲルマニウム（Ge）

To establish the technology of a strained Ge channel, after stressor formation, the dependences of strain on geometric and thermal treatment parameters were investigated by Raman spectroscopy. Defect generation, transformation, and distribution were also clarified by photoluminescence. To fabricate Ge-MOSFET, an ultra-thin SiO2/GeO2bilayer Ge-surface passivation method was developed without vacuum breaking, which showed a low interface states density (Dit) in the same degree of that for SiO2/Si. To eliminate the influence of slow-traps in the SiO2/GeO2structure, a deep level transient spectroscopy method was developed with optimized bias condition at each fixed-temperature, by which an accurate Ditevaluation was performed for GeO2/Ge. According to the result of strain evaluation, a good-quality Ge-MOSFET should be fabricated at a temperature less than 500 oC. Therefore, a low-temperature process was developed for Ge-MOSFET fabrication, by which the operation of Ge transistors was approved. Particularly, the channel mobility of p-MOSFET was four times higher than that of a Si transistor.

为了建立应变Ge沟道技术，在应力源形成后，利用拉曼光谱研究了应变与几何参数和热处理参数的关系。用光致发光分析了缺陷的产生、转变和分布。为了制备Ge-MOSFET，提出了一种无需真空破裂的超薄SiO_2/GeO_2双层Ge表面钝化方法，该方法具有与SiO_2/Si相同程度的低界面态密度(DIT)。为了消除SiO_2/GeO_2结构中慢陷阱的影响，建立了一种深能级瞬变光谱方法，并对每个恒温下的偏置条件进行了优化，从而对GeO_2/Ge进行了准确的Dit值计算。根据应变评估的结果，在低于500℃的温度下可以制作出高质量的Ge-MOSFET。为此，开发了一种用于Ge-MOSFET制作的低温工艺，从而验证了Ge晶体管的运行。特别是，p-MOSFET的沟道迁移率比硅晶体管高四倍。

项目成果

High Hole-Mobility Ge p-MOSFET with HfGe Schottky Source/Drain

具有 HfGe 肖特基源极/漏极的高空穴迁移率 Ge p-MOSFET

• 发表时间: 2012
• 期刊: Extended Abstracts of the 2012 International Conference on Solid State Devices and Materials
• 作者: T. Sada;K. Yamamoto;H. Yang;D. Wang;H. Nakashima
• 通讯作者: H. Nakashima

Fabrication of TiN/Si Contact with Low Electron Barrier Height and Electrical Characterization of Si-On-Insulator Using Back- Gate MOSFET

低电子势垒高度的 TiN/Si 接触的制造以及使用背栅 MOSFET 的绝缘体上硅的电气特性

• 发表时间: 2012
• 期刊: Extended Abstracts of the 2012 International Conference on Solid State Devices and Materials
• 作者: K. Asakawa;K. Yamamoto;D. Wang;H. Nakashima
• 通讯作者: H. Nakashima

High-quality gate-stack formation on Ge and defect termination at the interface

在 Ge 上形成高质量栅堆叠并在界面处终止缺陷

• 发表时间: 2011
• 作者: H. Nakashima;K. Hirayama;K. Yamamoto;H. Yang;D. Wang
• 通讯作者: D. Wang

Al/Ti/Snを用いたp形4H-SiCへのオーミックコンタクトの低温形成

使用 Al/Ti/Sn 低温形成 p 型 4H-SiC 欧姆接触

• 发表时间: 2013
• 作者: 畑山紘太;山本圭介;王冬;中島寛
• 通讯作者: 中島寛

極薄GeOX界面層を有するY2O3/Ge ゲートスタックの低温形成

具有超薄GeOX界面层的Y2O3/Ge栅叠层的低温形成

• 发表时间: 2013
• 作者: 永冨雄太;小島秀太;亀沢翔;山本圭介;王冬;中島寛
• 通讯作者: 中島寛