SoC Defect Level Reduction Based on Critical Area Sampling

在半导体器件制造领域中，在设计阶段估计的缺陷水平与制造的器件的报告缺陷水平之间存在差距的问题日益严重。在本文中，我们讨论了在目标电路的逻辑和布局结构的基础上，考虑故障概率的准确缺陷水平估计。我们提出并评估了三种方案：考虑多个不同缺陷尺寸的加权故障覆盖率计算，测试模式重排序算法，以及没有版图数据的关键区域估计。实验结果表明，我们提出的方案可以准确地估计真实的缺陷水平，也可以减少测试模式的数量。

In the field of semiconductor device manufacturing, there is growing problem of the gap between the defect level estimated at the design stage from the reported one for fabricated devices. In this we discuss on a accurrate defect levelestimation considering probability of faults, on the basis of logical and layout structures of target circuits. We proposed and evaluated three schemes: weighted fault coverage calculation considering multiple different defect sizes, test pattern reordering algorithm, and critical area estimation without layout data. Experimental results indicated that our proposed schemes can accurately estimate the real defect level, and also that the numbers of test patterns can be reduced.