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Research on the Hardware Mechanism to Assist Software based Caohe Coherence Schemes

基于漕河相干方案的硬件辅助软件机制研究

基本信息

批准号：
09680334
负责人：
MORI Shin-ichiro
金额：
$ 2.18万
依托单位：
KYOTO UNIVERSITY
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (C)
财政年份：
1997
资助国家：
日本
起止时间：
1997 至 1999
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-09680334/
关键词：
Distributed Shared Memory Cache Coherency Controll Parallel Processing Network Computer NCC-NUMA CC-NUMA Self Cleanup Cache NCC-MUMA CC-MUMA ネットワーク共有メモリ

项目摘要

In order to investigate the essential ability of the Non-Cache-Coherent NUMA system configured with write-back cache, we assumed an NCC-NUMA Architecture configured with Self-Cleanup Cache, which has an ability to enforce the write back of unused dirty line without invalidating the line, and evaluated its performance by simulation works.The result of the simulation showed that 1) NCC-NUMA System can achieve comparable performance to CC-NUMA system if some moderate optimizations are forced to the application program, 2) NCC-NUMA System outperforms CC-NUMA System if the network latency arrives to the order of 100 processor cycle, and 3) the performance gain of NCC-NUMA System to CC-NUMA System increases with the increase of the network latency for the well optimized application programs.We also found that, however, for some programs which were optimized to increase the memory access locality with the techniques like privatization or blocking, the self-invalidation and the self-cleanup of shared data placed in the local memory have a possibility of affecting the performance.To deal with this problem, we have proposed the Self-Cleanup Cache with 2bit Directory Scheme. By configuring a 2bit directory with each local memory and maintain the local caching status, intra-node cache coherence in this system is maintained like the other directory based system, so that unnecessary invalidations and self-cleanups of locally cached data disappear. After further study of this scheme, we found that the Self-Cleanup Cache with 2bit Directory Scheme is well applicable to the SMP Cluster system, which adopts the one-chip multiprocessor in particular.

为了研究配置回写缓存的非缓存一致NUMA系统的基本能力，我们假设一个配置了自清理缓存的NCC-NUMA体系结构，它能够强制回写未使用的脏行而不会使该行无效，并通过仿真工作评估其性能。仿真结果表明：1)对应用程序进行适度优化后，NCC-NUMA系统可以达到与CC-NUMA系统相当的性能；2)当网络延迟达到100个处理器周期数量级时，NCC-NUMA系统优于CC-NUMA系统；3)在优化后的应用程序中，NCC-NUMA系统相对于CC-NUMA系统的性能增益随着网络延迟的增加而增加。然而，我们还发现，对于一些通过私有化或阻塞等技术进行优化以增加内存访问局部性的程序，放置在本地内存中的共享数据的自我失效和自我清理有可能影响性能。为了解决这个问题，我们提出了自清理缓存与2位目录方案。通过为每个本地内存配置一个2bit目录并保持本地缓存状态，该系统中的节点内缓存一致性与其他基于目录的系统一样得到了维护，从而消除了本地缓存数据的不必要的失效和自清理。通过对该方案的进一步研究，我们发现2bit目录自清理缓存方案特别适用于采用单片多处理器的SMP集群系统。