Study of the implementation method for Newral Network Argoritm with a Multi-Context Dynamically Reconfigurable FPGA

本文提出了一种多上下文动态可重构FPGA的实现方法，并给出了一种优化使用多上下文动态可重构FPGA的CAD算法。多上下文动态可重构FPGA是一种可以在系统运行过程中进行编程的VLSI，其重构时间效率比传统的可重构FPGA要高。通过对多上下文动态可重构FPGA硬件描述的综合结果，对增加多上下文动态可重构FPGA的硬件代价进行了评估。通过与传统可重构FPGA的比较，评估了神经网络算法的实现对可配置逻辑块（CLB）或总线使用率的改善。多上下文FPGA的CAD算法最大限度地减少了与重构数据量成比例的重构时间开销。它输入一个有限状态机，输出状态子集，称为页面，这是多上下文FPGA的重配置单元。实验证明了该算法的性能。

In this study, We propose an implementation method of a Multi-Context Dynamically Reconfigurable FPGA and a CAD algorithm for optimal use of it. Multi-Context Dynamically Reconfigurable FPGA is a VLSI which can be programmed during system operation with better reconfiguration time-efficiency than conventional Reconfigurable FPGA. We evaluated the hardware cost to add the Multi-Context Dynamically Reconfigurable FPGA by the result of synthesis of the hardware description of the Multi-Context Dynamically Reconfigurable FPGA. And We also evaluated the improvement of CLB (Configurable Logic Block) or bus usage by the implementation of the Neural Network Algorithm compared with conventional Reconfigurable FPGA. The CAD algorithm for Multi-Context FPGA minimizes reconfiguration time overhead proportional to the amount of the reconfiguration data. It inputs a finite state machine and outputs subsets of states called pages which is a reconfiguration unit of Multi-Context FPGA. The performance of the proposed algorithm is demonstrated experimentally.