Study of the implementation method for Newral Network Argoritm with a Multi-Context Dynamically Reconfigurable FPGA

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In this study, We propose an implementation method of a Multi-Context Dynamically Reconfigurable FPGA and a CAD algorithm for optimal use of it. Multi-Context Dynamically Reconfigurable FPGA is a VLSI which can be programmed during system operation with better reconfiguration time-efficiency than conventional Reconfigurable FPGA. We evaluated the hardware cost to add the Multi-Context Dynamically Reconfigurable FPGA by the result of synthesis of the hardware description of the Multi-Context Dynamically Reconfigurable FPGA. And We also evaluated the improvement of CLB (Configurable Logic Block) or bus usage by the implementation of the Neural Network Algorithm compared with conventional Reconfigurable FPGA. The CAD algorithm for Multi-Context FPGA minimizes reconfiguration time overhead proportional to the amount of the reconfiguration data. It inputs a finite state machine and outputs subsets of states called pages which is a reconfiguration unit of Multi-Context FPGA. The performance of the proposed algorithm is demonstrated experimentally.