Compiling for Energy Efficiency in Multicore Memory Hierarchies

在过去的几年里，处理器制造商已经从单核设计转向多核架构。在这些新设备中，两个或更多处理核心被放置在单个芯片上，并链接在一起，以使几个应用程序能够完全同时运行。当前多核架构的示例包括英特尔酷睿2Quad和Cell宽带引擎。在每个处理核心上，可以相互并行运行多个执行线程。每个线程只是来自程序的指令流，必须以特定的顺序执行，以便执行特定的任务。例如，一个线程可能正在浏览器中加载网页，而另一个线程正在播放一些音乐。制造商正在依靠这种线程级并行来保持过去40年来在每一代新处理器中实现的性能提升。然而，功率效率仍然是处理器行业的一个主要问题，因为制造商寻求最大限度地利用芯片上的晶体管，以低能耗提供高性能。高速缓存层次结构是多核系统的一个元素，在该系统中，解决这些挑战可以产生显著的差异。高速缓存是一种快速存储器，通常位于与处理核心本身相同的芯片上。每个高速缓存存储频繁使用的指令和数据的副本，以便处理器可以轻松地访问它，而不是必须等待缓慢的片外存储器。高速缓存占据了总芯片面积的很大一部分，因此消耗了总系统功率的很大比例。在这里，线程也相互交互，竞争资源并消耗大量电能。该建议寻求通过使用编译器来提高能效来解决这些问题。编译器是将程序从人类可读的格式转换为在实际机器上运行的1和0的工具。在此过程中，它执行一些分析和优化，以使程序尽可能快地运行。该提案将考虑编译器在编译和运行时推断的知识的影响，从而能够生成能够自动影响底层环境节能的节能程序。该提案将考虑两个互补的项目主题：二级缓存管理和D-NUCA设计。第一个将考虑节能方案，该方案可以将部分二级高速缓存置于低功率休眠模式。编译器将具有使用状态保存(即，数据被保留)和状态销毁(即，数据丢失)技术的能力，并使用编译器在粗粒度(例如，每个高速缓存体)和更精细的级别(例如，高速缓存线)关闭高速缓存的部分。本研究的第二个主题将考虑一种新兴的高速缓存体系结构：D-NUCA(Dynamic Non-Uniform Cache Architecture)设计。顾名思义，这种类型的缓存访问其中的不同数据具有可变的延迟。这一建议将开发一种技术来影响缓存的数据管理策略，以保持该范例的高性能和灵活性，同时还提供静态能量降低的机会。此外，该计划将主动利用现有的数据迁移基础设施，在有益的情况下在缓存中移动某些信息，以增加静态节能。

Over the past few years, processor manufacturers have switched from single core designs to multicore architectures. In these new devices, two or more processing cores are placed on a single chip and linked together to enable several applications to run at exactly the same time. Examples of current multicore architectures include the Intel Core 2 Quad and the Cell Broadband Engine.On each processing core, several threads of execution can run in parallel with each other. Each thread is simply a stream of instructions from a program that must be executed in a particular order so that a certain task is performed. For example, one thread might be loading up a web page in a browser whilst another is playing some music. Manufacturers are relying on this thread-level parallelism to maintain the performance gains that have been achieved in each new generation of processors over the last 40 years. However, power efficiency continues to be a major issue for the processor industry as manufacturers seek to maximise the usage of the transistors on-chip, delivering high performance with low energy.The cache hierarchy is one element of a multicore system where tackling these challenges can make a significant difference. A cache is a fast memory, usually on the same chip as the processing cores themselves. Each cache stores a copy of the frequently used instructions and data so that the processor has easy access to it, instead of having to wait for a slow, off-chip memory. The caches occupy a significant fraction of the total chip area and thus consume a large percentage of the total system power. Here also, threads interact with each other, competing for resources and consuming a significant amount of electrical energy.This proposal seeks to address these issues by using the compiler to drive energy efficiency. The compiler is the tool that converts a program from a human-readable format into the 1s and 0s that run on the actual machine. Along the way it performs some analysis and optimisation to make the program run as fast as possible. This proposal will consider the impact of compiler-inferred knowledge during compilation and runtime, enabling the generation of energy-efficient programs that can automatically influence energy saving in the underlying environment.The proposal will consider two complementary project themes: level 2 cache management and D-NUCA designs. The first will consider energy saving schemes that can place parts of the second level cache into low power sleep modes. The compiler will have the ability to use both state-preserving (i.e. the data is retained) and state-destroying (i.e. the data is lost) techniques and use the compiler to turn off parts of the cache at both a coarse granularity (e.g. each cache bank) and at a finer level too (e.g. cache lines). This work will consider the trade-offs between static energy savings and increased dynamic energy consumption through extra cache misses.The second topic in this research will consider an emerging cache architecture: D-NUCA (Dynamic Non-Uniform Cache Architecture) designs. As the name suggests, this type of cache has a variable latency to access different data within it. This proposal will develop a technique to influence the data management policy of the cache to maintain the high performance and flexibility of this paradigm, yet also provide opportunities for static energy reduction. Furthermore, the scheme will proactively leverage the existing data migration infrastructure to move certain information around the cache, when beneficial, for increased static energy savings.