M3: Managing Many-Cores for the Masses

M3：为大众管理多核

• 批准号: EP/K026399/1
• 负责人: Timothy Jones
• 金额: $ 154.47万
• 依托单位: University of Cambridge
• 依托单位国家: 英国
• 项目类别: Fellowship
• 财政年份: 2013
• 资助国家: 英国
• 起止时间: 2013 至 无数据
• 项目状态: 已结题
• 来源: https://gtr.ukri.org/projects?ref=EP%2FK026399%2F1
• 关键词: M3; Managing; Many; Cores; Masses

Since the invention of the microprocessor in the early 1970s, information and communication technologies have rapidly improved almost all aspects of our daily lives. Unrelenting growth in computing power has been the enabler for significant scientific advances and transformed our society in the way we work, play and interact with each other. Fundamentally, this has been achieved through continuous strides in semiconductor technology, repeatedly doubling the number of transistors available on a chip every 18 months (famously known as Moore's Law). At the same time, Dennard scaling ensured that overall chip power and area stayed constant, allowing computer architects to design more and more elaborate processors to take advantage of the increased transistor counts and provide faster and faster systems.All this was performed transparently to the programmer, who simply had to switch to a new processor to make his applications run faster. There was no need to rewrite or modify parts of the program, or worry about the characteristics of the underlying platform. There was, in effect, a contract between the hardware and software, whereby the architect would provide more advanced systems and the programmer would concentrate on producing more sophisticated and innovative applications.Serendipitous transistor scaling couldn't last forever though, and in the early part of this century we hit the "power wall". Transistors could no longer be made smaller yet achieve the same power efficiency gains as in previous technology generations. In response, industry switched to multicore designs, aiming to continue performance increases through thread-level parallelism. This, in effect, broke the contract, requiring software writers to create programs with an eye on performance, as well as functionality. Although there are some application domains that can benefit from this parallelism (e.g. games), there is little evidence that developers have risen to the challenge of writing multi-threaded code and even when they do, the runtime environment doesn't necessarily allow their threads to actually be executed in parallel.The failure of Dennard scaling means that many-core chips are the logical next step. However, it also means that the energy problem will not decline, and key industry figures warn of "dark silicon" when we have abundant transistors on chip but lack the ability to power them all on at once. We may soon find that significant parts of each multicore chip must be turned off, due to power limitations. Added to this, as transistors shrink they become more susceptible to manufacturing variability, wearout and in-field faults, decreasing their reliability and shortening the lifespan of the systems they construct. Unless we take drastic action, this convergence of challenges could seriously undermine our ability to continue advancing the systems that have revolutionised our lives.This fellowship is a step towards meeting these challenges by reinstating the hardware / software contract, allowing the system to deal with each issue and leaving the application developer free to continue innovating. It will bring together a world-class research team that will investigate a variety of holistic schemes to achieve this aim based on automatic parallelisation, heterogeneous architectures and optical networks-on-chip, directly tackling the challenges laid out in the EPSRC cross-ICT priority of Many-Core Architectures and Concurrency in Distributed and Embedded Systems.

自20世纪70年代初微处理器发明以来，信息和通信技术迅速改善了我们日常生活的几乎所有方面。计算能力的不断增长推动了重大的科学进步，并改变了我们的社会，改变了我们的工作、娱乐和互动方式。从根本上说，这是通过半导体技术的不断进步实现的，每18个月芯片上可用的晶体管数量就翻一番（著名的摩尔定律）。与此同时，Dennard缩放确保了整个芯片的功率和面积保持不变，允许计算机架构师设计越来越复杂的处理器，以利用增加的晶体管数量，提供越来越快的系统。所有这些都是对程序员透明的，程序员只需切换到新的处理器，就可以让他的应用程序运行得更快。不需要重写或修改程序的某些部分，也不需要担心底层平台的特性。实际上，硬件和软件之间有一个契约，即架构师将提供更先进的系统，程序员将专注于生产更复杂和创新的应用程序。然而，偶然的晶体管缩放不可能永远持续下去，在本世纪早期，我们撞上了“电源墙”。晶体管不能再做得更小，但能实现与前几代技术相同的功率效率增益。作为回应，业界转向多核设计，旨在通过线程级并行继续提高性能。这实际上打破了合同，要求软件作者在创建程序时不仅要考虑功能，还要考虑性能。虽然有一些应用领域可以从这种并行性中受益（例如游戏），但几乎没有证据表明开发人员已经接受了编写多线程代码的挑战，即使他们这样做了，运行时环境也不一定允许他们的线程实际上并行执行。Dennard扩展的失败意味着众核芯片是合乎逻辑的下一步。然而，这也意味着能源问题不会下降，关键的行业人士警告说，当我们在芯片上有大量的晶体管，但缺乏同时为它们供电的能力时，就会出现“暗硅”。我们可能很快就会发现，由于功率限制，每个多核芯片的重要部分都必须关闭。除此之外，随着晶体管的缩小，它们变得更容易受到制造可变性、磨损和现场故障的影响，从而降低了它们的可靠性并缩短了它们构建的系统的寿命。除非我们采取激烈的行动，否则这些挑战的汇集可能会严重削弱我们继续推进已经彻底改变我们生活的系统的能力。这项奖学金是通过恢复硬件/软件合同来应对这些挑战的一步，允许系统处理每个问题，并让应用程序开发人员自由地继续创新。它将汇集一个世界级的研究团队，该团队将研究各种整体方案，以基于自动并行化、异构架构和片上光网络实现这一目标，直接解决EPSRC跨ICT多核优先级中提出的挑战分布式和嵌入式系统中的核心架构和并发性。

项目成果

An Event-Triggered Programmable Prefetcher for Irregular Workloads

针对不规则工作负载的事件触发可编程预取器

• DOI: 10.1145/3173162.3173189
• 发表时间: 2018
• 作者: Ainsworth S

ParaMedic: Heterogeneous Parallel Error Correction

ParaMedic：异构并行纠错

• DOI: 10.1109/dsn.2019.00032
• 发表时间: 2019
• 作者: Ainsworth S

Software prefetching for indirect memory accesses: A microarchitectural perspective

间接内存访问的软件预取：微架构视角

• DOI: 10.17863/cam.38025
• 发表时间: 2019
• 作者: Ainsworth S

ParaDox: Eliminating Voltage Margins via Heterogeneous Fault Tolerance

• DOI: 10.1109/hpca51647.2021.00051
• 发表时间: 2021-02
• 期刊: 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA)
• 作者: S. Ainsworth;Lionel Zoubritzky;A. Mycroft;Timothy M. Jones

Graph Prefetching Using Data Structure Knowledge

• DOI: 10.1145/2925426.2926254
• 发表时间: 2016-06
• 期刊: Proceedings of the 2016 International Conference on Supercomputing
• 作者: S. Ainsworth;Timothy M. Jones