ParaSol: Fine-Grained Thread-Level Parallelism for Single-Threaded Performance

自世纪之交以来，多核处理器已经在几乎所有的计算领域变得司空见惯。性能不再仅仅来自指令级并行性（ILP）的提取，它现在还要求软件开发人员或编译器将应用程序分解为多个指令流，以利用粗粒度线程级并行性（TLP）。虽然单线程性能对大型程序非常有益，但它仍然非常重要，特别是在执行速度可以支配整个程序性能的应用程序的顺序部分（有时被称为“Amdahl的残酷法则”）。此外，单线程性能的改进对所有应用程序都有好处，因为每个线程都会经历性能提升，从而影响代码的所有部分——顺序的和并行的。然而，提高单线程性能是很困难的。向多核的转变是由复杂无序硬件方案的功率限制所驱动的，以提取ILP（由底层晶体管技术中的Dennard缩放失败引起）。虽然设计师仍然增加了无序指令窗口，但不幸的是，这只会产生微小的差异，未来的设计预计将受到波拉克规则和ILP的基本限制（ILP墙）的限制。相反，尽管许多应用程序可以通过利用TLP大幅提升性能，但实际上提取它仍然是一个挑战（John Hennessy说编写并行代码是“一个与计算机科学面临的任何问题一样困难的问题”）。这个项目采用了一种完全不同的方法。它没有带着无序执行的复杂方案回到未来，而是探索了现代多核利用的ILP和粗粒度TLP之间的空间。特别是，它侧重于从内核内部和跨内核的单个指令流中提取细粒度的TLP。一方面，它将研究对应用程序透明地识别和启动独立的短时间运行线程（硬件线程）的方案，从而提高单线程性能。另一方面，它将研究编译器技术来表明这种并行性，硬件能够在多个紧密耦合的内核内部和跨内核利用这种并行性。如果成功，该项目将导致高性能核心性能的逐步变化，这是由核心资源利用率的提高和以可扩展的方式增加这些资源的能力所驱动的。它还将开辟更广阔的设计空间，用更高的TLP取代无序的管道复杂性，在面积、效率和应用领域适用性之间找到更好的平衡。

Since the turn of the century, multicore processors have become commonplace in almost all computing domains. Instead of performance coming solely from the extraction of instruction-level parallelism (ILP), it now also requires software developers or compilers to break applications into multiple streams of instructions to exploit coarse-grained thread-level parallelism (TLP). Whilst extremely beneficial for a large class of programs, single-threaded performance still matters greatly, especially during sequential parts of an application where execution speed can dominate overall program performance (sometimes dubbed "Amdahl's cruel law"). In addition, improvements in single-threaded performance benefit all applications, as each thread experiences a performance uplift, thus impacting all parts of the code-sequential and parallel.However, improving single-threaded performance is hard. The move to multicore was driven by the power limitations of complex out-of-order hardware schemes to extract ILP (caused by the failure of Dennard scaling in the underlying transistor technologies). While designers do still increase the out-of-order instruction window, unfortunately this only makes a marginal difference and future designs are expected to be limited by Pollack's rule and the fundamental limits of ILP (the ILP wall). Conversely, although many applications would see a major performance boost from taking advantage of TLP, actually extracting it remains a challenge (John Hennessy said writing parallel code is "a problem that's as hard as any that computer science has faced").This project takes a radically different approach. Instead of going back to the future with elaborate schemes for out-of-order execution, it explores the space between ILP and the coarse-grained TLP exploited by modern multicores. In particular, it focuses on the extraction of fine-grained TLP from a single stream of instructions within and across cores. On the one hand it will investigate schemes to identify and spin-up independent short-running threads (hardware threadlets) transparently to the application, so as to boost single-threaded performance. On the other, it will research compiler techniques to indicate this parallelism, with the hardware able to exploit it within and across multiple tightly coupled cores. If successful, this project would lead to a step change in performance of high-performance cores, driven by increased utilisation of core resources and the ability to increase those resources in a scalable manner. It would also open up a broader design space, trading out-of-order pipeline complexity for ILP with increased TLP, to find better balances between area, efficiency and application-domain suitability.