Multiscale Modelling of Metal-Semiconductor Contacts for the Next Generation of Nanoscale Transistors

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Contacts, made up of metal-semiconductor interfaces, are integral parts any semiconductor device. Compatibility of the metal and semiconductor components, homogeneity of structural and electrical characteristics of their interfaces, and robustness and durability of the contacts are crucial for the device proper functionality.Optimal operation of the contacts is a key to realisation of novel devices and development of new device concepts, including high mobility semiconductors based CMOS, tunnelling and spin-based transistors, tunnelling diodes, gas and infrared carbon-nanotube detectors, etc. Two major current trends in the semiconductor industry - miniaturisation of the devices and shift to new materials - pose the challenges for the contact technology: (i) robustness and stability of operation in ever smaller devices and (ii) compatibility of metal and semiconductor components. For example, the resistance of present day contacts is strongly affected by fluctuations in the currently being developed sub-22 nm technology. This problem is getting worse for smaller devices. On the other hand, introduction of new materials for high-mobility channels, e.g., Ge and III-Vs, necessitates the search for compatible metals and brings new challenges related to the contact fabrication. Therefore, understanding the dependence of the nanoscale metal-semiconductor interface properties on the atomic structure of this interface, chemical composition disorder, and defects is a key to formulating and exploiting new device concepts. In particular, this understanding is imperative for the developing of optimal contact fabrication procedures for nano-scale semiconductor devices.Primary aims of the proposed research are i) enabling and carrying out multiscale modelling of the optimal chemical compositions and structures of metal-semiconductor interfaces such that the Schottky barrier is minimal;ii) analysis of the role of interface defects, strain, and disorder on the carrier transport in CMOS devices.We will first develop a methodology which bridges ab initio simulations of atomic-scale structures and electronic properties of interfaces at 1-3 nm scale and simulation of device current-voltage characteristics at the scale of 5-50 nm. The results of the ab initio calculations will be transferred into 3D Monte Carlo (MC) transport simulations, which will allow us to make a realistic representation of the metal-semiconductor interface and develop a physical model of source/drain contacts. This model, in turn, will be incorporated into a 2D MC device simulator to predict the device performance and thus allow one for the straightforward comparison with experimental data obtained directly from the operating devices. Such methodology will allow us: i) to consider explicitly effects of point defects (<0.5 nm scale), composition disorder (~1 nm scale), and metal granularity (~1-2 nm scale) on the electronic properties of selected metal-semiconductor interfaces, ii) to incorporate these effects into 3D MC transport simulations through the metal-semiconductor interfaces,iii) to develop realistic models for source/drain contacts, carry out 2D MC device simulations, and to optimise device performance with respect to the properties of the contacts.The methodology will be first tested on the case of Ti metal contact with an archetypal III-V semiconductor GaAs and the results will be validated using experimental data provided by our project partners. Then other systems of increasing complexity will be investigated: interfaces of Ti metal with unary Si and Ge, doped GaAs, and ternary InGaAs semiconductors and, finally, interfaces of TiN metal alloy with InGaAs. Our theoretical predictions will be validated by and compared to experimental results at each scale: Transmission Electron Microscopy (TEM) data for the interface structures, resistance measurements for the transport through the interface, I-V characteristics for the device simulations.