Multiscale Modelling of Metal-Semiconductor Contacts for the Next Generation of Nanoscale Transistors

触点由金属-半导体接口组成，是任何半导体器件的组成部分。金属和半导体组件的兼容性，其接口的结构和电气特性的均匀性，以及触点的坚固性和耐用性对于设备的正常功能至关重要。触点的最佳操作是实现新器件和新器件概念发展的关键，包括基于高迁移率半导体的CMOS，隧穿和自旋晶体管，隧穿二极管，气体和红外碳纳米管探测器等。半导体工业当前的两个主要趋势——器件的小型化和向新材料的转变——对接触技术提出了挑战：(1)在越来越小的器件中运行的稳健性和稳定性；(2)金属和半导体元件的兼容性。例如，当前触点的电阻受到当前正在开发的sub-22 nm技术波动的强烈影响。对于小型设备来说，这个问题变得越来越严重。另一方面，引入用于高迁移率通道的新材料，例如Ge和iii - v，需要寻找兼容的金属，并带来与接触制造相关的新挑战。因此，了解纳米级金属-半导体界面性能与该界面的原子结构、化学成分紊乱和缺陷的依赖关系是制定和开发新器件概念的关键。特别是，这种理解对于开发纳米级半导体器件的最佳接触制造工艺是必不可少的。所提出的研究的主要目的是i)实现并进行金属-半导体界面的最佳化学成分和结构的多尺度建模，使肖特基势垒最小；ii)分析界面缺陷、应变和无序对CMOS器件载流子输运的影响。我们将首先开发一种方法，将1-3纳米尺度上原子尺度结构和界面电子特性的从头模拟与5-50纳米尺度上器件电流-电压特性的模拟联系起来。从头计算的结果将被转移到三维蒙特卡罗（MC）输运模拟中，这将使我们能够真实地表示金属-半导体界面，并开发源/漏接触的物理模型。反过来，该模型将被纳入2D MC设备模拟器，以预测设备性能，从而允许与直接从操作设备获得的实验数据进行直接比较。这种方法将使我们：i)明确考虑点缺陷（<0.5 nm尺度）、成分无序（~1 nm尺度）和金属粒度（~1-2 nm尺度）对所选金属-半导体界面电子特性的影响，ii)将这些影响纳入通过金属-半导体界面的3D MC输运模拟，iii)开发源/漏触点的真实模型，进行2D MC器件模拟。并根据触点的特性优化设备性能。该方法将首先在Ti金属与原型III-V半导体GaAs接触的情况下进行测试，结果将使用我们的项目合作伙伴提供的实验数据进行验证。然后将研究其他越来越复杂的系统：Ti金属与一元Si和Ge的界面，掺杂GaAs，三元InGaAs半导体，最后是TiN金属合金与InGaAs的界面。我们的理论预测将通过每个尺度的实验结果进行验证和比较：界面结构的透射电子显微镜（TEM）数据，通过界面传输的电阻测量，设备模拟的I-V特性。

Contacts, made up of metal-semiconductor interfaces, are integral parts any semiconductor device. Compatibility of the metal and semiconductor components, homogeneity of structural and electrical characteristics of their interfaces, and robustness and durability of the contacts are crucial for the device proper functionality.Optimal operation of the contacts is a key to realisation of novel devices and development of new device concepts, including high mobility semiconductors based CMOS, tunnelling and spin-based transistors, tunnelling diodes, gas and infrared carbon-nanotube detectors, etc. Two major current trends in the semiconductor industry - miniaturisation of the devices and shift to new materials - pose the challenges for the contact technology: (i) robustness and stability of operation in ever smaller devices and (ii) compatibility of metal and semiconductor components. For example, the resistance of present day contacts is strongly affected by fluctuations in the currently being developed sub-22 nm technology. This problem is getting worse for smaller devices. On the other hand, introduction of new materials for high-mobility channels, e.g., Ge and III-Vs, necessitates the search for compatible metals and brings new challenges related to the contact fabrication. Therefore, understanding the dependence of the nanoscale metal-semiconductor interface properties on the atomic structure of this interface, chemical composition disorder, and defects is a key to formulating and exploiting new device concepts. In particular, this understanding is imperative for the developing of optimal contact fabrication procedures for nano-scale semiconductor devices.Primary aims of the proposed research are i) enabling and carrying out multiscale modelling of the optimal chemical compositions and structures of metal-semiconductor interfaces such that the Schottky barrier is minimal;ii) analysis of the role of interface defects, strain, and disorder on the carrier transport in CMOS devices.We will first develop a methodology which bridges ab initio simulations of atomic-scale structures and electronic properties of interfaces at 1-3 nm scale and simulation of device current-voltage characteristics at the scale of 5-50 nm. The results of the ab initio calculations will be transferred into 3D Monte Carlo (MC) transport simulations, which will allow us to make a realistic representation of the metal-semiconductor interface and develop a physical model of source/drain contacts. This model, in turn, will be incorporated into a 2D MC device simulator to predict the device performance and thus allow one for the straightforward comparison with experimental data obtained directly from the operating devices. Such methodology will allow us: i) to consider explicitly effects of point defects (<0.5 nm scale), composition disorder (~1 nm scale), and metal granularity (~1-2 nm scale) on the electronic properties of selected metal-semiconductor interfaces, ii) to incorporate these effects into 3D MC transport simulations through the metal-semiconductor interfaces,iii) to develop realistic models for source/drain contacts, carry out 2D MC device simulations, and to optimise device performance with respect to the properties of the contacts.The methodology will be first tested on the case of Ti metal contact with an archetypal III-V semiconductor GaAs and the results will be validated using experimental data provided by our project partners. Then other systems of increasing complexity will be investigated: interfaces of Ti metal with unary Si and Ge, doped GaAs, and ternary InGaAs semiconductors and, finally, interfaces of TiN metal alloy with InGaAs. Our theoretical predictions will be validated by and compared to experimental results at each scale: Transmission Electron Microscopy (TEM) data for the interface structures, resistance measurements for the transport through the interface, I-V characteristics for the device simulations.