Multiscale Modelling of Metal-Semiconductor Contacts for the Next Generation of Nanoscale Transistors

下一代纳米级晶体管金属-半导体接触的多尺度建模

• 批准号: EP/I010084/1
• 负责人: Karol Kalna
• 金额: $ 36.95万
• 依托单位: Swansea University
• 依托单位国家: 英国
• 项目类别: Research Grant
• 财政年份: 2011
• 资助国家: 英国
• 起止时间: 2011 至 无数据
• 项目状态: 已结题
• 来源: https://gtr.ukri.org/projects?ref=EP%2FI010084%2F1
• 关键词: Multiscale; Modelling; Metal; Semiconductor; Contacts

Contacts, made up of metal-semiconductor interfaces, are integral parts any semiconductor device. Compatibility of the metal and semiconductor components, homogeneity of structural and electrical characteristics of their interfaces, and robustness and durability of the contacts are crucial for the device proper functionality.Optimal operation of the contacts is a key to realisation of novel devices and development of new device concepts, including high mobility semiconductors based CMOS, tunnelling and spin-based transistors, tunnelling diodes, gas and infrared carbon-nanotube detectors, etc. Two major current trends in the semiconductor industry - miniaturisation of the devices and shift to new materials - pose the challenges for the contact technology: (i) robustness and stability of operation in ever smaller devices and (ii) compatibility of metal and semiconductor components. For example, the resistance of present day contacts is strongly affected by fluctuations in the currently being developed sub-22 nm technology. This problem is getting worse for smaller devices. On the other hand, introduction of new materials for high-mobility channels, e.g., Ge and III-Vs, necessitates the search for compatible metals and brings new challenges related to the contact fabrication. Therefore, understanding the dependence of the nanoscale metal-semiconductor interface properties on the atomic structure of this interface, chemical composition disorder, and defects is a key to formulating and exploiting new device concepts. In particular, this understanding is imperative for the developing of optimal contact fabrication procedures for nano-scale semiconductor devices.Primary aims of the proposed research are i) enabling and carrying out multiscale modelling of the optimal chemical compositions and structures of metal-semiconductor interfaces such that the Schottky barrier is minimal;ii) analysis of the role of interface defects, strain, and disorder on the carrier transport in CMOS devices.We will first develop a methodology which bridges ab initio simulations of atomic-scale structures and electronic properties of interfaces at 1-3 nm scale and simulation of device current-voltage characteristics at the scale of 5-50 nm. The results of the ab initio calculations will be transferred into 3D Monte Carlo (MC) transport simulations, which will allow us to make a realistic representation of the metal-semiconductor interface and develop a physical model of source/drain contacts. This model, in turn, will be incorporated into a 2D MC device simulator to predict the device performance and thus allow one for the straightforward comparison with experimental data obtained directly from the operating devices. Such methodology will allow us: i) to consider explicitly effects of point defects (<0.5 nm scale), composition disorder (~1 nm scale), and metal granularity (~1-2 nm scale) on the electronic properties of selected metal-semiconductor interfaces, ii) to incorporate these effects into 3D MC transport simulations through the metal-semiconductor interfaces,iii) to develop realistic models for source/drain contacts, carry out 2D MC device simulations, and to optimise device performance with respect to the properties of the contacts.The methodology will be first tested on the case of Ti metal contact with an archetypal III-V semiconductor GaAs and the results will be validated using experimental data provided by our project partners. Then other systems of increasing complexity will be investigated: interfaces of Ti metal with unary Si and Ge, doped GaAs, and ternary InGaAs semiconductors and, finally, interfaces of TiN metal alloy with InGaAs. Our theoretical predictions will be validated by and compared to experimental results at each scale: Transmission Electron Microscopy (TEM) data for the interface structures, resistance measurements for the transport through the interface, I-V characteristics for the device simulations.

由金属-半导体界面组成的接触是任何半导体器件的组成部分。金属和半导体元件的兼容性、其界面结构和电气特性的均匀性以及接触的坚固性和耐用性对于器件的正常功能至关重要。接触的优化操作是实现新颖器件和开发新器件概念的关键，包括基于高迁移率半导体的 CMOS、隧道和自旋晶体管、隧道二极管、气体和半导体器件。 半导体行业当前的两大趋势——器件的小型化和向新材料的转变——对接触技术提出了挑战：(i) 在更小的器件中运行的稳健性和稳定性；(ii) 金属和半导体元件的兼容性。例如，当前触点的电阻受到当前正在开发的 22 纳米以下技术波动的强烈影响。对于较小的设备，这个问题变得更加严重。另一方面，引入用于高迁移率通道的新材料（例如Ge和III-V族）需要寻找兼容的金属，并带来与接触制造相关的新挑战。因此，了解纳米级金属-半导体界面特性对该界面原子结构、化学成分无序和缺陷的依赖性是制定和开发新器件概念的关键。特别是，这种理解对于开发纳米​​级半导体器件的最佳接触制造工艺至关重要。所提出的研究的主要目的是i）实现并进行金属-半导体界面的最佳化学成分和结构的多尺度建模，以使肖特基势垒最小化；ii）分析界面缺陷、应变和无序对载流子传输的作用 CMOS器件。我们将首先开发一种方法，将1-3 nm尺度的原子尺度结构和界面电子特性的从头模拟与5-50 nm尺度的器件电流-电压特性的模拟结合起来。从头计算的结果将被转移到 3D 蒙特卡罗 (MC) 传输模拟中，这将使我们能够真实地表示金属-半导体界面并开发源极/漏极接触的物理模型。反过来，该模型将被纳入 2D MC 设备模拟器中，以预测设备性能，从而可以与直接从操作设备获得的实验数据进行直接比较。这种方法将使我们能够：i) 明确考虑点缺陷（<0.5 nm 尺度）、成分无序（~1 nm 尺度）和金属粒度（~1-2 nm 尺度）对选定金属-半导体界面的电子特性的影响，ii) 将这些影响纳入通过金属-半导体界面的 3D MC 传输模拟中，iii) 开发源极/漏极接触的真实模型，执行 2D MC 器件模拟，并根据接触特性优化器件性能。该方法将首先在 Ti 金属与典型 III-V 半导体 GaAs 接触的情况下进行测试，结果将使用我们的项目合作伙伴提供的实验数据进行验证。然后将研究复杂性不断增加的其他系统：Ti 金属与一元 Si 和 Ge、掺杂 GaAs 和三元 InGaAs 半导体的界面，最后是 TiN 金属合金与 InGaAs 的界面。我们的理论预测将通过各个尺度的实验结果进行验证和比较：界面结构的透射电子显微镜 (TEM) 数据、界面传输的电阻测量、器件模拟的 I-V 特性。

项目成果

Multi-scale simulations of a Mo/ n + -GaAs Schottky contact for nano-scale III-V MOSFETs

纳米级 III-V MOSFET 的 Mo/ n -GaAs 肖特基接触的多尺度模拟

• DOI: 10.1088/0268-1242/29/5/054003
• 发表时间: 2014
• 期刊: Semiconductor Science and Technology
• 影响因子: 1.9
• 作者: Aldegunde M

3D Monte Carlo study of scaled SOI FinFETs using 2D Schrödinger quantum corrections

使用 2D 薛定谔量子校正对缩放 SOI FinFET 进行 3D 蒙特卡罗研究

• DOI: 10.1109/ulis.2014.6813925
• 发表时间: 2014
• 作者: Elmessary M

Device and Circuit Performance of the Future Hybrid III-V and Ge-Based CMOS Technology

未来混合 III-V 和基于 Ge 的 CMOS 技术的器件和电路性能

• DOI: 10.1109/ted.2016.2603188
• 发表时间: 2016
• 期刊: IEEE Transactions on Electron Devices
• 影响因子: 3.1
• 作者: Benbakhti B

Influence of device geometry on electrical characteristics of a 10.7 nm SOI-FinFET

器件几何形状对 10.7 nm SOI-FinFET 电气特性的影响

• DOI: 10.1109/iwce.2014.6865877
• 发表时间: 2014
• 作者: Abdikarimov A

Multi-scale Simulations of Metal-Semiconductor Nanoscale Contacts

• DOI: 10.1088/1742-6596/647/1/012030
• 发表时间: 2015-10
• 期刊: Journal of Physics: Conference Series
• 作者: M. Aldegunde;S. Hepplestone;P. Sushko;K. Kalna