Modelling of Carrier Transport in Ultra Thin Body Transistors

国际半导体技术路线图（International Technology Roadmap for Semiconductors）要求对常规金属氧化物半导体场效应晶体管进行积极的缩放，因为常规器件将达到超过45 nm技术节点的极限。为了保持器件性能的预期增长，必须将新型超薄体晶体管引入生产。此外，硅元件的本体和二氧化硅介电质均须以更高迁移率的半导体和更高介电常数的材料取代。建议的研究金旨在开发一种“最先进”的蒙特卡罗器件模拟器，能够准确模拟超薄体晶体管的低维特性。该模拟器将用于优化超薄体结构，对未来的高迁移率材料进行基准测试，并研究高K值对沟道迁移率的影响。它还将侧重于开发不同的材料晶体取向的通道。随附的研究资助提案旨在建立一个新的蒙特卡罗模拟工具，并增强合作者在纳米线晶体管研究中使用的非平衡绿色函数模拟器。

Aggressive scaling of the conventional metal-oxide-semiconductor field effect transistors is required by the International Technology Roadmap for Semiconductors as conventional devices will hit a limit beyond the 45 nm technology node. Novel, ultra-thin body transistors must be introduced into production in order to sustain the expected increase in device performance. Moreover, both the Silicon device body and the SiO2 dielectric have to be replaced with a higher mobility semiconductor and higher dielectric constant materials.The proposed fellowship research aims to develop a 'state-of-art' Monte Carlo device simulator which is capable of accurately modelling the low-dimensional properties of ultra-thin body transistors. The simulator will be employed to optimise the ultra-thin body architecture, to benchmark the prospective high mobility materials, and to investigate the impact of high-K dielectrics on channel mobility. It will also focus on the exploitation of different material crystal orientations in the channel. The accompanying research grant proposal aims to establish a new Monte Carlo simulation tool and enhancing the collaborators' Non-Equilibrium Green Functions simulator employed in the investigation of nanowire transistors.