权益分类	功能权益	普通用户	{{item.name}}会员
{{category.name}}	{{benefitItem.name}}

Mixed Criticality Embedded Systems on Many-Core Platforms

多核平台上的混合关键嵌入式系统

基本信息

批准号：
EP/K011626/1
负责人：
Alan Burns
金额：
$ 83.09万
依托单位：
University of York
依托单位国家：
英国
项目类别：
Research Grant
财政年份：
2013
资助国家：
英国
起止时间：
2013 至无数据
项目状态：
已结题

来源：
https://gtr.ukri.org/projects?ref=EP%2FK011626%2F1
关键词：
Mixed Criticality Embedded Systems Many

项目摘要

An increasingly important trend in the design of real-time and embedded systems is the integration of applications with different levels of criticality onto a common hardware platform. At the same time, these platforms are migrating from single cores to multi-cores and, in the future, many-core architectures. Criticality is a designation of the level of assurance against failure needed for a system component. A mixed criticality system (MCS) is one that has two or more distinct levels. A number of application domains, such as automotive and avionics, and EU initiatives (for example Horizon2020) have identified Mixed Criticality as a key issue in future systems.The fundamental research question underlying these initiatives is: how, in a disciplined way, to reconcile the conflicting requirements of 'partitioning' for (safety) assurance and 'sharing' for efficient resource usage. This question gives rise to theoretical problems in modelling and verification, and systems problems relating to the design and implementation of the necessary hardware and software run-time controls. This project addresses both the theoretical and related systems questions.A many-core platform with a scheduled communications medium is the designated platform on which multiple applications (perhaps composed of what are often called 'system of systems') are to be hosted. The isolation of components with different criticality levels is crucial, but the processor interconnects must be shared and be able to transmit messages with different criticality levels. Moreover, applications with different criticality levels must be able to exchange data in a demonstrably safe way.A defining property of MCS is that the different means of assurance (for each criticality level) give rise to different values for the component's key parameters such as worst-case execution times and worst-case transmission times. In general, the higher the criticality level, the more conservative are the assumptions made about these values. Hence the context (system criticality level) will determine the parameters that must be used to verify (via scheduling analysis) that each core and each inter-connect will perform as required by the temporal constraints of each application. The development of criticality-aware analysis is needed for these systems.Although total isolation with rigid time-triggered global scheduling is a possible architectural structure, significantly greater resource utilisation and hence reduced power consumption is possible if trade-offs are made between the overall system criticality level and assumptions about each component's run-time behaviour. For example, we require that: in a dual-criticality systems all applications will meet their timing constraints if all components are constrained by (rely on) their low criticality assumptions, but all high-criticality applications must also meet their deadlines if any component exhibits high-criticality behaviour (i.e. the low criticality assumptions can no longer be relied upon).Previous work (in York and in a number of other international research centres) has explored this trade-off for single processor systems. This project will focus on many-core platforms to: (i) develop the appropriate scheduling schemes (on the cores and interconnects), (ii) derive verification procedures for MCSs, (iii) explore the theoretical bounds of the developed schemes (to show to what extent resource usage and power consumption are improved over a full partitioned system), (iv) develop the necessary run-time controls (to manage the sharing of communication media between the criticality levels), and (v) demonstrate the developed theory via simulations, a FPGA test-bed and an industrially relevant case study.

在实时和嵌入式系统的设计中，一个越来越重要的趋势是将具有不同关键程度的应用程序集成到一个通用的硬件平台上。与此同时，这些平台正在从单核迁移到多核，将来还会迁移到众核架构。关键性是系统组件所需的故障保证级别的指定。混合关键度系统（MCS）是一个有两个或两个以上不同级别的系统。许多应用领域，如汽车和航空电子，和欧盟的倡议（例如地平线2020）已确定混合关键性作为一个关键问题，在未来systems.the基本的研究问题，这些倡议是：如何，在一个有纪律的方式，以协调冲突的要求“分区”（安全）保证和“共享”的有效资源的使用。这个问题引起的理论问题，在建模和验证，以及系统的问题有关的设计和实施必要的硬件和软件运行时的控制。这个项目解决了理论和相关的系统问题。一个具有预定通信介质的多核平台是多个应用程序（可能由通常称为“系统的系统”组成）托管的指定平台。具有不同关键性级别的组件的隔离是至关重要的，但是处理器互连必须是共享的，并且能够传输具有不同关键性级别的消息。此外，具有不同关键性级别的应用程序必须能够以可证明安全的方式交换数据。MCS的一个定义属性是，不同的保证手段（针对每个关键性级别）会导致组件关键参数的不同值，例如最坏情况下的执行时间和最坏情况下的传输时间。一般来说，临界水平越高，对这些值的假设就越保守。因此，上下文（系统关键性级别）将确定必须用于验证（通过调度分析）每个核心和每个互连将按照每个应用程序的时间约束的要求执行的参数。这些systems.Although严格的时间触发的全局调度完全隔离是一种可能的架构结构，显着更大的资源利用率，从而降低功耗是可能的，如果权衡之间的整体系统的关键性水平和假设每个组件的运行时的行为。例如，我们要求：在双关键性系统中如果所有组件都受到（依赖于）它们的低关键性假设的约束，但是，如果任何部件表现出高关键性行为，则所有高关键性应用也必须满足其截止日期（即不再依赖低关键性假设）。（在约克和其他一些国际研究中心）已经探索了单处理器系统的这种权衡。该项目将侧重于众核平台，以便：（i）制订适当的排期计划（核心和互连），（ii）推导出MCS的验证程序，（iii）探索所开发方案的理论界限（为了示出在全分区系统上资源使用和功耗被改进到什么程度），（iv）开发必要的运行时控制（以管理关键性级别之间的通信介质共享），以及（v）通过模拟、FPGA测试台和工业相关案例研究来演示所开发的理论。