Development of micro-thermal dividers for hybrid pixel detectors coupling cryogenic HPGe sensors and room temperature ASICs.

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This project is proposing a new, unproven and disruptive technology to enable the application of High Purity germanium (HPGe) sensors with existing room temperature Application Specific Integrated Circuits (ASICs) in hybrid pixel detectors. It is proposed to design and test a micro-thermal divider translating the physics requirements set by the Fourier's Law of heat conduction, into an engineered solution exploiting the capabilities offered by micro-fabrication and micro-machining processes, and by micro-electronics interconnection techniques. The micro-thermal divider will control a challenging delta T of ~130deg C over few 100's um. The hybrid pixel detectors prototyped in this project will target mainly applications in photon-science. Here, hybrid pixel detectors provide high performance solutions for X-ray detection by combining direct photon detection, small pixel size, fast readout and sophisticated signal processing circuitry in each pixel. For X-ray detection above 20 keV, high-Z sensors different than silicon are required to achieve high quantum efficiency, but many high-Z materials such as GaAs, CdTe and CdZnTe often suffer from unfavourable material properties or nonuniformities. Remarkably, HPGe crystals provide a unique combination of favourable crystal properties and material purity that translates into a high, uniform detection efficiency and an excellent energy resolution, over a large area (wafers ~90mm dia.). The deployment of HPGe sensors in hybrid pixel detectors is currently limited by the cryogenic requirements of the sensors, which is usually linked to the development of cryogenic ASICs. These are niche, complex and costly developments. Instead, we propose a shift of paradigm in the existing thought by studying the effectiveness of micro-technologies to replace the need of cryogenic ASICs for high-energy radiation detection instrumentation. To achieve this, a micro-thermal divider will be inserted between the sensor and the ASIC. It will insulate the sensor from the heat generated by the ASIC, and it will provide direct cooling underneath the sensor.The high-risk and speculative aspect of the project is related to managing a high temperature gradient (~130deg C) over a short distance (100's um), while maintaining an excellent electrical performance and mechanical stability of the device. The ambition of this bid is to build a functional prototype demonstrating the feasibility of the technology (proof of concept), and generating foundation work for the next iteration, where a fully engineered device will be built.The main aim of the project is to position the UK in a leadership role to build the next generation of hybrid pixel detectors for flagship synchrotron and free electron laser experiments. We want to develop an innovative technique to operate HPGe sensors with room temperature ASICs. High-end applications like nuclear medical imaging applications (detecting gamma-rays) and X-rays spectral molecular imaging would also be beneficiaries of this technological progress, which has the potential to improve the quality of diagnostics in healthcare. There is an energy saving aspect related to this proposed solution. The operating temperature of a room temperature ASIC would require less cooling power than an equivalent cryogenic ASIC. This would contribute to reduce the carbon footprint while developing cutting edge instrumentation based on HPGe sensors. The analogy of satellite operations with in-vacuum thermal management/energy efficiency via micro thermal-dividers could lead to more efficient thermal control systems for space instrumentation. Finally, R&D on a micro thermal-divider has synergies with the field of quantum computing. Here, our approach could be used to develop new packaging solutions for the quantum-to-classical interface in a cryogenic environment with multiple temperature stages. For instance, this could benefit quantum computers based on superconducting qubits.