Silicon-based Fault-Tolerant Quantum Computing

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Quantum computation has just entered a new era, that of Noisy Intermediate-Scale Quantum (NISQ) technologies in which quantum processors are able to perform calculations beyond the capabilities of the world's greatest supercomputers. This remarkable achievement sets an important milestone in quantum computing (QC) and brings focus towards the ultimate goal of the QC roadmap: building a fault-tolerant quantum machine. A machine with sufficient error-free computing resources to run quantum algorithms with the potential to radically transform society. Algorithms that will help us better forecast weather and financial markets, speed up searches in unsorted databases, essential for the Big Data era, and most importantly, accelerate the pace of discovery of new materials and medicines, so relevant for the times we live in. The most promising routes to fault-tolerant QC will require quantum error correction (QEC) to enable accurate computing despite the intrinsically noisy nature of the individual quantum bits constituting the machine. The idea is based on distributing the logical information over a number of physical qubits. As long as the physical qubits satisfy a maximum error rate (1% for the most forgiving method, the surface code) fault-tolerance can be achieved. The exact physical qubit overhead (per logical qubit) depends on the error rate but considering state-of-the-art qubit fidelities, it will likely be a figure in excess of a hundred. QEC is then expected to take the number of required physical qubits to many thousands for economically significant algorithms and to many millions for some of the more demanding quantum computing applications. Scaling is hence a generic scientific and technological challenge.Building qubits based on the spin degree of freedom of individual electrons in silicon nanodevices offers numerous advantages over competing technologies such as the scalability of the most compact solid-state approach and the extensive industrial infrastructure of silicon transistor technology devoted to fabricating multi-billion-element integrated circuits. Besides, silicon electron spin qubits are one of the most coherent systems in nature, characteristic that has enabled demonstrating all the operational steps - initialization, control and readout - with sufficient level of precision for fault-tolerant computing. However, most of the results achieved so far come from devices fabricated in academic cleanrooms with relatively low level of reproducibility and in one- or two-qubit processors at best [Huang et al. Nature 569, 532]. But the recent demonstration of a single hole spin qubit [Maurand et al Nat Commun 7 13575] and electron spin control and readout in devices fabricated in a 300 mm complementary metal-oxide-semiconductor (CMOS) platform open an opportunity to trigger a transition from lab-based proof-of-principle experiments to manufacturing qubits at scale [Gonzalez-Zalba et al, Physics World (2019)]. In the project SiFT, I will build on my pioneering work on CMOS-based quantum computing [Nat Commun 6 6084, Nat Elect 2 236, Nat Nano 14 437] to demonstrate, for the first time, all the necessary steps to run the surface code. I will target a two-dimensional qubit lattices where arbitrary quantum errors could be detected and corrected making clusters of qubits more reliable that the individual constituents. My quantum circuit designs will be manufactured in experimental and commercial silicon foundries that use very large-scale integration processes. The project will be the steppingstone towards building in the UK a large-scale silicon-based quantum processor with sufficient error-free computational resources to make an impact on society. It will help take QC beyond NISQ into the fault-tolerant era where the computational promises of QC can be fully exploited.