Silicon-based Fault-Tolerant Quantum Computing

量子计算刚刚进入了一个新时代，噪声中尺度量子(NISQ)技术，在这个时代，量子处理器能够执行超出世界上最大超级计算机能力的计算。这一非凡的成就为量子计算(QC)树立了一个重要的里程碑，并使人们将注意力集中在QC路线图的最终目标上：构建容错量子机。一台具有足够的无错误计算资源的机器，可以运行具有从根本上改变社会的潜力的量子算法。算法将帮助我们更好地预报天气和金融市场，加快对未排序数据库的搜索，这对大数据时代至关重要，最重要的是，加快发现与我们所处时代如此相关的新材料和药物的步伐。最有希望实现容错QC的方法将需要量子纠错(QEC)来实现准确计算，尽管构成机器的单个量子比特本质上存在噪声。这个想法是基于将逻辑信息分布在多个物理量子比特上。只要物理量子比特满足最大误码率(最大容错率为1%，表面码)，就可以实现容错。确切的物理量子比特开销(每个逻辑量子比特)取决于错误率，但考虑到最先进的量子比特保真度，它可能会超过100。然后，预计QEC将把具有重要经济意义的算法所需的物理量子比特数量提高到数千个，并将一些要求更高的量子计算应用程序提高到数百万个。因此，规模化是一个普遍的科学和技术挑战。在硅纳米器件中基于单个电子的自旋自由度来构建量子比特，与竞争技术相比具有许多优势，例如最紧凑的固态方法的可扩展性，以及致力于制造数十亿元素集成电路的硅晶体管技术的广泛工业基础设施。此外，硅电子自旋量子比特是自然界中最连贯的系统之一，这一特性使我们能够以足够的精度演示所有操作步骤--初始化、控制和读出--以进行容错计算。然而，到目前为止取得的大多数结果来自于在学术洁净室中制造的设备，其重复性相对较低，最多只有一到两个量子比特处理器[Huang等人。大自然569,532]。但最近的单洞自旋量子比特[Maurand等人NAT Commun 7 13575]演示以及在300 mm互补金属氧化物半导体平台上制造的设备中的电子自旋控制和读出打开了一个机会，可以触发从基于实验室的原理验证实验到大规模制造量子比特的转变[Gonzalez-Zalba等人，物理世界(2019年)]。在SIFT项目中，我将在我对基于CMOS的量子计算[NAT Commun 6 6084，NAT Elect 2 236，NAT Nano 14 437]的开创性工作的基础上，首次演示运行表面代码的所有必要步骤。我将以二维量子比特格为目标，在那里可以检测和纠正任意的量子误差，使量子比特集群比单个成分更可靠。我的量子电路设计将在实验和商业硅铸造厂制造，这些工厂使用非常大规模的集成工艺。该项目将是在英国建立大规模硅基量子处理器的踏脚石，该处理器具有足够的无错误计算资源，可以对社会产生影响。它将帮助QC超越NISQ进入容错时代，在这个时代，QC的计算承诺可以得到充分利用。

Quantum computation has just entered a new era, that of Noisy Intermediate-Scale Quantum (NISQ) technologies in which quantum processors are able to perform calculations beyond the capabilities of the world's greatest supercomputers. This remarkable achievement sets an important milestone in quantum computing (QC) and brings focus towards the ultimate goal of the QC roadmap: building a fault-tolerant quantum machine. A machine with sufficient error-free computing resources to run quantum algorithms with the potential to radically transform society. Algorithms that will help us better forecast weather and financial markets, speed up searches in unsorted databases, essential for the Big Data era, and most importantly, accelerate the pace of discovery of new materials and medicines, so relevant for the times we live in. The most promising routes to fault-tolerant QC will require quantum error correction (QEC) to enable accurate computing despite the intrinsically noisy nature of the individual quantum bits constituting the machine. The idea is based on distributing the logical information over a number of physical qubits. As long as the physical qubits satisfy a maximum error rate (1% for the most forgiving method, the surface code) fault-tolerance can be achieved. The exact physical qubit overhead (per logical qubit) depends on the error rate but considering state-of-the-art qubit fidelities, it will likely be a figure in excess of a hundred. QEC is then expected to take the number of required physical qubits to many thousands for economically significant algorithms and to many millions for some of the more demanding quantum computing applications. Scaling is hence a generic scientific and technological challenge.Building qubits based on the spin degree of freedom of individual electrons in silicon nanodevices offers numerous advantages over competing technologies such as the scalability of the most compact solid-state approach and the extensive industrial infrastructure of silicon transistor technology devoted to fabricating multi-billion-element integrated circuits. Besides, silicon electron spin qubits are one of the most coherent systems in nature, characteristic that has enabled demonstrating all the operational steps - initialization, control and readout - with sufficient level of precision for fault-tolerant computing. However, most of the results achieved so far come from devices fabricated in academic cleanrooms with relatively low level of reproducibility and in one- or two-qubit processors at best [Huang et al. Nature 569, 532]. But the recent demonstration of a single hole spin qubit [Maurand et al Nat Commun 7 13575] and electron spin control and readout in devices fabricated in a 300 mm complementary metal-oxide-semiconductor (CMOS) platform open an opportunity to trigger a transition from lab-based proof-of-principle experiments to manufacturing qubits at scale [Gonzalez-Zalba et al, Physics World (2019)]. In the project SiFT, I will build on my pioneering work on CMOS-based quantum computing [Nat Commun 6 6084, Nat Elect 2 236, Nat Nano 14 437] to demonstrate, for the first time, all the necessary steps to run the surface code. I will target a two-dimensional qubit lattices where arbitrary quantum errors could be detected and corrected making clusters of qubits more reliable that the individual constituents. My quantum circuit designs will be manufactured in experimental and commercial silicon foundries that use very large-scale integration processes. The project will be the steppingstone towards building in the UK a large-scale silicon-based quantum processor with sufficient error-free computational resources to make an impact on society. It will help take QC beyond NISQ into the fault-tolerant era where the computational promises of QC can be fully exploited.