Power-Adaptive Computing: Run-Time Management Design on FPGA SoC Devices

传统的嵌入式系统的低功耗设计方法集中于提供性能驱动的设计，其中通过放松任务的执行时间来实现节能，同时满足实时截止日期。传统的设计策略不能再确保在不同功率水平下运行的新兴无处不在的系统中的计算确定性，例如在环境能源中看到的。由于动态功率行为，系统的稳定性和计算进度无法得到保证，特别是当再次发生功率波动或功率预算不足可能终止任务的完成并降低应用质量时。因此，这需要设计新的运行时管理解决方案，这将允许设计通用系统，其中软件和硬件句柄能够有效地将可用能量转换为计算能力，并在动态功率分布下保证任务保持或完成。基于异构CPU-GPU的系统可以实现各种性能和能量权衡，但是当能量稀缺时，通过高度定制的硬件，如FPGA或ASIC，可以实现相同级别的功能。用于逻辑设计的高级综合工具的能力不断提高，应用程序开发时间不断缩短，这使得FPGA SoC对定制设计很有吸引力。离线功率估计工具允许通过模拟电路来确定概率系统功耗。然而，这种方法不能提供足够的信息，系统的功率行为在运行时。复杂的设计需要深入了解子系统级功耗。因此，在高层应用层提供这些信息，并结合自适应运行时算法和功耗管理技术，将有助于设计节能和功耗自适应的应用。本研究的关键是建立一种智能的功耗自适应运行时管理，其自主地做出计算决策，以减轻计算不确定性并保证由输入电平调制的连续功能权力为此，将通过分析和建模从内置硬件监视器获得的数据来引入功率感知功能，以便制定功率预算。在运行时调度计算任务的决定将使用机器学习算法与电源管理技术（如电压频率缩放）相结合来促进。该研究项目旨在开发一种工具来支持功率自适应系统的设计，其中计算操作由运行时例程管理，以在能量或功率约束内调制未来的计算。

Traditional low-power design methodologies of embedded systems have focused on delivering performance-driven designs, where energy savings are achieved by relaxing execution time of tasks, while meeting the real-time deadlines. Conventional design strategies cannot longer ensure the computational certainty in emerging ubiquitous systems operating under varying levels of power, such as seen in ambient energy sources. Due to dynamic power behaviour, the stability and the computational progress of systems cannot be guaranteed, particularly when re-occurring power fluctuations or insufficient power budgets can terminate the completion of tasks and degrade the quality of applications. Therefore, this necessitates to design new runtime management solutions, which would allow to design versatile systems, where software and hardware handles are capable of effectively converting the available energy into computing power and guarantee task retention or completion under dynamic power profile.Heterogeneous CPU-GPU based systems can achieve various performance and energy trade-offs, but when the energy is scarce, the same level of functionality can be achieved through highly customized hardware, such as FPGAs or ASICs. The increasing capabilities of high-level synthesis tools for logic design and shorter application development time makes FPGA SoCs appealing for custom designs. Offline power estimation tools allow to determine probabilistic system power consumption by simulating circuits. However, such approach cannot provide enough information about system's power behaviour at run-time. Complex designs require in-depth knowledge about sub-system level power usage. Therefore, provided with such information at high-level application layer and combined with adaptive run-time algorithms together with power management techniques, it would facilitate the design of energy-efficient and power-adaptive applications.The key of this research is to establish an intelligent power-adaptive run-time management, which autonomously makes computing decisions in order to mitigate the computational uncertainties and warrant continuous functionality modulated by the incoming levels of power. For this purpose, the power-awareness feature will be introduced by analysing and modelling data obtained from a built-in hardware monitors, in order to formulate the power budgets. The decision to schedule computing tasks at run-time will be facilitated using machine learning algorithms coupled with power management techniques, such as voltage-frequency scaling. The research project is intended to develop a tool to support the design of power-adaptive systems, where the computing actions are governed by the run-time routines to modulate future computations within the energy or power constrain.