Developing fabrication processes for optoelectronic integration

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The development of new fabrication strategies is required for integrated optoelectronics. For example, there are challenges in etching facets for III-phosphide materials, and III-P and / or III-As on Silicon where the combination of CS and silicon leads to different requirements. In integrated devices the processes to deposit high reflectivity mirrors on facets or layers providing surface passivation and increases in the catastrophic optical facet damage level are not straightforward. SPTS have tools that can etch facets and they have processes that can deposit conformal layers on surface and surface normal surfaces. These processes may hugely benefit the performance of integrated devices and so the project is about developing these processes for lasers, as an example of the most sensitive active component, while being appropriate for full scale integrated optoelectronic circuits.There may also be advantages for individual devices or small scale integrated chips if we can combine a high quality etched facet process with a wafer segmentation process. These are developed for silicon but the Compound Semiconductor materials and devices may suffer substantial or subtle damage from these processes as currently utilised.InAs Quantum Dot materials grown on an GaAs lattice constant (on Silicon) are said to offer some tolerance to damage created in active devices and we will examine whether the InAs quantum dots on an InP lattice constant (on Silicon) also offer such advantages and how these compare to quantum well active devices and how both compare to e.g. cleaved facet and /or scribed devices.