Neural network topologies from a hardware perspective

从硬件角度看神经网络拓扑

• 批准号: 2748013
• 金额: --
• 依托单位: Imperial College London
• 依托单位国家: 英国
• 项目类别: Studentship
• 财政年份: 2022
• 资助国家: 英国
• 起止时间: 2022 至 无数据
• 项目状态: 未结题
• 来源: https://gtr.ukri.org/projects?ref=studentship-2748013
• 关键词: Neural; network; topologies; hardware; perspective

At the core of the current industrial revolution lies the growth of machine learning algorithms: especially Deep Neural Networks (DNNs) [1]. DNNs are widely used for a vast number of artificial intelligence (AI) tasks, including computer vision, speech recognition, and natural language processing. The problem I strive to address is that state-of-the-art DNNs reach high accuracy at the expense of large computational complexity [1]. Machine learning researchers aim to design architectures to improve accuracy, without focusing on the inference cost [1]. I aspire to investigate DNN architectures from both machine learning and hardware design automation perspectives. My goal is to bridge the gap between the research in the neural network field and custom hardware field, to push the limits of the trade-off between accuracy and computational cost.E. Wang et al. [2] analysed how DNNs' algorithmic advancement favours specialised hardware and showed how Field Programmable Gate Arrays (FPGAs) reach superior performance in comparison to alternative platforms. I am driven to study the capabilities of and resources available in FPGA platforms and gain deeper understanding of DNN topological design to take full advantage of the hardware when thinking about the design of the algorithms for Deep Learning.The underlying FPGA architecture consists of K-input Boolean Lookup Tables (LUTs). To take advantage of the flexibility provided by these LUTs, E. Wang et al. [3] introduced LUTNet, the first neural network architecture featuring K-input LUTs as inference operators. It was shown that taking advantage of the potential of the LUTs and their capabilities results in the possibility of heavier network pruning, and thus significant area reduction, while maintaining accuracy [3].Binary Neural Networks (BNNs) address the high computational cost of neural networks and the infeasibility of deployment on memory-constrained platforms. Prof. G. Constantinides [4] explains why BNNs are not universally able to reach as high accuracy compared with networks with other data representations. The reason does not lie within the generality of the data representation, but rather in the traditional design technique that is unable to adapt the topology of the network to the underlying datatype. Hence, moving forward, we need to find a way to adapt the neural network topology to both the data and the nature of the discrete representation of activations. Therefore, the possibility of valuable topological research is identified by considering "Boolean circuits as neural networks".The question I would initially like to find the answer for is: What network topologies are best suited for LUTNet and what further modifications to LUTNet or the topology itself would lead to further efficiency? To answer the question, I would try to investigate what are the problems that come up in hardware, for example, long critical paths, high fan-in/-out or memory constraints and find existing/developing new topologies that address these problems. Following, I would explore what modifications would benefit the design, these modifications coming from both machine learning and hardware perspectives.

当前工业革命的核心在于机器学习算法的发展：尤其是深度神经网络（DNN）[1]。 DNN 广泛用于大量人工智能 (AI) 任务，包括计算机视觉、语音识别和自然语言处理。我努力解决的问题是，最先进的 DNN 以巨大的计算复杂性为代价来达到高精度 [1]。机器学习研究人员的目标是设计架构来提高准确性，而不关注推理成本 [1]。我渴望从机器学习和硬件设计自动化的角度研究 DNN 架构。我的目标是弥合神经网络领域和定制硬件领域的研究之间的差距，突破准确性和计算成本之间权衡的极限。王等人。 [2] 分析了 DNN 的算法进步如何有利于专用硬件，并展示了现场可编程门阵列 (FPGA) 与替代平台相比如何实现卓越的性能。我致力于研究 FPGA 平台的功能和可用资源，并深入了解 DNN 拓扑设计，以便在考虑深度学习算法设计时充分利用硬件。底层 FPGA 架构由 K 输入布尔查找表 (LUT) 组成。为了利用这些 LUT 提供的灵活性，E. Wang 等人。 [3] 介绍了 LUTNet，这是第一个以 K 输入 LUT 作为推理算子的神经网络架构。结果表明，利用 LUT 的潜力及其功能可以实现更重的网络修剪，从而显着减少面积，同时保持精度 [3]。二元神经网络 (BNN) 解决了神经网络计算成本高以及在内存受限平台上部署的不可行性问题。 G. Constantinides 教授 [4] 解释了为什么与其他数据表示的网络相比，BNN 普遍无法达到那么高的准确度。原因不在于数据表示的通用性，而在于传统的设计技术无法使网络拓扑适应底层数据类型。因此，展望未来，我们需要找到一种方法，使神经网络拓扑适应数据和激活离散表示的性质。因此，通过考虑“布尔电路作为神经网络”来确定有价值的拓扑研究的可能性。我最初想找到答案的问题是：什么网络拓扑最适合LUTNet，以及对LUTNet或拓扑本身的哪些进一步修改会带来更高的效率？为了回答这个问题，我会尝试调查硬件中出现的问题，例如长关键路径、高扇入/出或内存限制，并找到解决这些问题的现有/正在开发的新拓扑。接下来，我将探讨哪些修改将对设计有利，这些修改来自机器学习和硬件的角度。