Communication Centric Microelectronic Design

我们希望研究以通信为中心的微电子设计方法，这与今天以计算为中心（或门级）的技术形成对比。我们认为这项研究是及时的，因为电子产品正处于变革的风口浪尖。在过去的60年里，数字门的生产成本很高，而且性能有限。我们现在正在进入一个时代，曾经几乎免费的电线成为成本和性能的限制因素。这一趋势在国际半导体技术路线图（ITRS）路线图中有很好的记录，该路线图清楚地确定了电路和相关设计技术所需的阶跃变化。他们还发现了螺旋式设计的复杂性、不断上升的功率密度和相关的热问题。我们相信片上网络解决了未来纳米CMOS实现技术的许多设计挑战。我们在该领域的背景研究已经产生了一种低延迟的片上网络架构，我们已经在180nm CMOS上制造了这种架构。最初的工作集中在我们与麻省理工学院共同开发的平铺式处理器架构之间的互连。然而，对于这个项目，我们希望走得更远，从cmochips上的ASIC设计到新的现场可编程门阵列（FPGA）架构，研究多层次和一系列技术的通信。FPGA架构偏离了我们通常的研究路线，因此我们特别荣幸地获得了Altera UK（两家大型国际FPGA公司之一）的全额资助博士学位，他们将与我们在这个项目上合作。

We wish to undertake research into communication centricmicroelectronic design methods which are in contrast to today'scomputation centric (or gate-level) techniques. We believe thatthis research is timely since electronics is at the cusp of change.For the last 60 years, digital gates have been costly to produce andhave limited performance. We are now entering an era where the wires,which were once almost free, becoming the cost and performancelimiter. This trend is well documented in the InternationalTechnology Roadmap for Semiconductors (ITRS) roadmap which clearlyidentifies the step change needed in circuits and associated designtechniques. They also identify spiralling design complexity,escalating power densities and associated thermal problems.We believe that networks-on-chip resolve many of the design challengesfor future nano CMOS implementation technologies. Our backgroundresearch in this area has already resulted in a low latencynetwork-on-chip architecture which we have fabricated on 180nm CMOS.This initial work focused on interconnect between a tiled processorarchitecture which we have been developing with MIT. However, forthis project we wish to go much further, looking at communication atmany levels and for a range of technologies, from ASIC design on CMOSchips through to new field programmable gate array (FPGA)architectures. FPGA architecture is a departure from our usual lineof research, so we have been particularly grantified to receivea fully funded PhD studentship from Altera UK (one of the two biginternational FPGA companies) who will collaborate with us on thisproject.