Advanced synthesiser techniques for mobile communications.

现代通信产品，从电视机到移动的电话，普遍使用一种称为频率合成器的电路来产生一系列频率，以允许产品调谐到不同的频道。在许多应用中，特别是在移动的通信中，这些合成器需要产生非常纯净的信号，同时能够快速改变信道。这些要求变得越来越苛刻，并且通常需要使用多个合成器回路以实现期望的性能。最近，开发了一种称为分数N合成的技术，仅使用单个合成器即可实现此功能-单回路解决方案。这可以非常快速地调谐，但往往是有噪声的，因此，已经应用了更先进的技术，特别是Σ-Δ调制，以尝试控制这种噪声。然而，这种方法在相位噪声（一种随机噪声）和离散分数杂散（单个音调）方面仍然存在问题。拟议的研究涉及三种独立技术的调查，每种技术都来自UCL的申请人，以提高单环频率合成器的性能，其目的是与当前的多环系统相媲美或超过该系统。这样做的好处将是一个简化，更紧凑，更经济的实施提供同样的高性能。由于这些电路被广泛使用，其商业影响可能相当大。第一种技术，称为存储序列合成，涉及通过计算用于控制环路分频器的所需位序列并将其存储在存储器中来模仿传统Σ-Δ小数N合成器的行为。然后以非常高的速度读出，以产生所需的分频比，从而产生信道频率。高速以及离线生成和优化位序列的能力，在频谱纯度和调谐速度方面提供了主要优势，并且应该比现有设计提供一个数量级的改进。拟议项目的第二部分建立在我们最近的开创性理论工作的互调效应在小数-N合成器，其中我们已经发现，自然现象（互调和混叠）的组合能够产生一个家庭的离散杂散在完全相同的频率，由于一个众所周知的机制，在不同的部分，系统的调制器。这表明，我们发现的现象可能是一个重要的和根本的性能限制，到目前为止已经完全被忽视;我们想比较我们的理论工作与实验结果从精心设计的测试电路，以确定这种机制的真正意义。这项工作可以提供机会来控制这种互调的影响，从而提高性能。拟议研究的最终目的是应用我们在电子系统非线性建模方面的经验，特别是Σ-Δ ADC（以前EPSRC奖的主题）和PLL中的混沌，开发一套通用工具，以获得优化的小数N频率合成器调制器设计，从而为目前的“切割和尝试”设计过程提供科学的解决方案。

Modern communications products, from TV sets to mobile phones, universally use a circuit known as a frequency synthesiser to generate a range of frequencies to allow the product to tune to different channels. In many applications, particularly mobile communications, these synthesisers need to produce very pure signals and simultaneously be able to change channels rapidly. These requirements are becoming increasingly demanding and often entail the use of multiple synthesiser loops in order to achieve the desired performance. More recently, a technique known as fractional-N synthesis has been developed to achieve this function using just a single synthesiser - a single-loop solution. This can tune very quickly, but tends to be noisy and, as a result, more advanced techniques have been applied, particularly sigma-delta modulation, to attempt to control this noise. However, there are still problems with this approach in terms of phase noise (a type of random noise) and discrete fractional spurs (individual tones).The proposed research involves investigation of three separate techniques, each originating from the applicants at UCL, to improve the performance of single-loop frequency synthesisers with the aim of rivalling or exceeding that of current multi-loop systems. The benefits of this would be a simplified, more compact and more economical implementation offering the same high performance. Since these circuits are very widely used, the commercial impact could be considerable. The first technique, known as stored-sequence synthesis, involves mimicking the behaviour of conventional sigma-delta fractional-N synthesisers by calculating the required bit sequences used to control the loop divider and storing them in memory. This is then read out at very high speed to produce the desired division ratio and hence channel frequency. The high speed and ability to generate and optimise the bit sequences off-line, offer major advantages in spectral purity and tuning speed and should provide an order of magnitude improvement over existing designs. The second part of the proposed project builds on our recent pioneering theoretical work on intermodulation effects in fractional-N synthesisers, in which we have discovered that a combination of natural phenomena (intermodulation and aliasing) are able to produce a family of discrete spurs at exactly the same frequencies as those due to a well known mechanism in a different part of the system, the modulator. This suggests that the phenomenon we have discovered may be an important and fundamental limitation on performance that has so far been completely overlooked; we would like to compare our theoretical work with experimental results from a carefully-designed test circuit to determine the true significance of this mechanism. This work may offer the opportunity to control the effects of such intermodulation and so improve performance. The final aim of the proposed research is to apply our experience in non-linear modelling of electronic systems, particularly sigma-delta ADCs (the subject of a previous EPSRC award) and chaos in PLLs, to develop a generic set of tools with which to obtain optimised fractional-N frequency synthesiser modulator designs and thus provide a scientific solution to what is currently something of a 'cut and try' design process.