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Novel nano-scale Screen-grid FET technology for ultra low power applications

适用于超低功耗应用的新型纳米级屏栅 FET 技术

基本信息

批准号：
EP/E023150/1
负责人：
Kristel Fobelets
金额：
$ 18.41万
依托单位：
Imperial College London
依托单位国家：
英国
项目类别：
Research Grant
财政年份：
2006
资助国家：
英国
起止时间：
2006 至无数据
项目状态：
已结题

来源：
https://gtr.ukri.org/projects?ref=EP%2FE023150%2F1
关键词：
Novel nano scale Screen grid

项目摘要

A novel planar Field Effect Transistor (FET) has been proposed with a 3D gating configuration that allows to minimise the deterioration of the characteristics of the FET when downscaling, a problem that hinders current FET technology. The FET is defined on Silicon on insulator (SOI) and is called Screen-Grid FET (SGFET) because of its analogy with tetrodes in vacuum tube technology.In this research we will first establish the operation parameters of the SGFET and investigate the influence of downscaling on both DC and AC characteristics. This will be done via the use of commercially available TCAD models such as Medici and Taurus (from Synopsis).In the second stage we will compare the operation of the novel SGFET with current FET technology such as fully-depleted FETs on SOI (FDSOI) and the finFET, also defined on SOI. This comparison, both for analog and digital applications, will be based on precisely defined benchmarking parameters.Finally we will evaluate critically the impact of the chosen mobility models on the operation of the devices. This will be done by introducing Monte Carlo generated mobility models into the TCAD environment that will enable a better electric field dependency of the carrier mobility in the 3D stucture.The result of this TCAD modelling will establish if the proposed 3D planar SGFET on SOI is a competitor for current novel FET structures structures such as finFETs and FDSOI MOSFETs. It will also establish the application domains in which the SGFET might outperform the current novel hightech devices. These domains can be analog and/or digital and low and/or full power applications.A positive outcome of the benchmarking exercise will prolong the lifetime of CMOS technology by 1) relaxing the need for agressive downscaling and 2) by disconnecting the geometry involved in downscaling from the parameters that lead to the deterioration of the device operation.

已经提出了一种新颖的具有3D选通配置的平面场效应晶体管（FET），该3D选通配置允许在缩小尺寸时最小化FET的特性的劣化，该劣化是阻碍当前FET技术的问题。场效应晶体管定义在绝缘体上硅（SOI）上，由于其类似于真空管技术中的四极管，因此被称为屏栅场效应晶体管（SGFET）。在本研究中，我们将首先建立SGFET的工作参数，并研究缩小尺寸对直流和交流特性的影响。这将通过使用商业上可用的TCAD模型来完成，例如Medici和Taurus（来自Synopsis）。在第二阶段，我们将比较新型SGFET与当前FET技术的操作，例如SOI上的全耗尽FET（FDSOI）和也定义在SOI上的finFET。这种比较，无论是模拟和数字应用，将基于精确定义的基准参数。最后，我们将严格评估所选择的移动模型对设备操作的影响。这将是通过引入Monte Carlo生成的迁移率模型到TCAD环境，这将使一个更好的电场依赖性的载流子迁移率在3D structure. This TCAD建模的结果将建立如果提出的SOI上的3D平面SGFET是目前的新颖的FET结构，如finFET和FDSOI MOSFET的结构的竞争对手。它还将建立SGFET可能优于当前新型高科技器件的应用领域。这些领域可以是模拟和/或数字以及低功率和/或全功率应用。基准测试的积极结果将通过以下方式延长CMOS技术的寿命：1）放松对积极降尺度的需求; 2）将降尺度中涉及的几何结构与导致器件操作恶化的参数断开。