Novel nano-scale Screen-grid FET technology for ultra low power applications

提出了一种新型的平面场效应晶体管（FET），具有3D门控配置，可以最大限度地减少FET在降尺度时特性的恶化，这是当前FET技术的一个阻碍问题。FET是在绝缘体上硅（SOI）上定义的，由于其类似于真空管技术中的四极管，因此被称为屏栅FET （SGFET）。在本研究中，我们将首先建立SGFET的工作参数，并研究降阶对直流和交流特性的影响。这将通过使用商业上可用的TCAD模型，如美第奇和金牛座（来自概要）来完成。在第二阶段，我们将比较新型SGFET与当前FET技术的工作，例如SOI上的全耗尽FET （FDSOI）和finFET，也定义在SOI上。这种比较，无论是模拟和数字应用，将基于精确定义的基准参数。最后，我们将批判性地评估所选择的移动模型对设备操作的影响。这将通过在TCAD环境中引入蒙特卡罗生成的迁移率模型来实现，这将使3D结构中的载流子迁移率具有更好的电场依赖性。该TCAD建模的结果将确定所提出的SOI上的三维平面SGFET是否与当前新型FET结构（如finfet和FDSOI mosfet）竞争。它还将建立SGFET可能优于当前新型高科技器件的应用领域。这些领域可以是模拟和/或数字和低和/或全功率应用。基准测试的积极结果将延长CMOS技术的使用寿命：1)减少对大幅降尺的需求；2)通过将降尺所涉及的几何形状与导致器件运行恶化的参数分离开来。

A novel planar Field Effect Transistor (FET) has been proposed with a 3D gating configuration that allows to minimise the deterioration of the characteristics of the FET when downscaling, a problem that hinders current FET technology. The FET is defined on Silicon on insulator (SOI) and is called Screen-Grid FET (SGFET) because of its analogy with tetrodes in vacuum tube technology.In this research we will first establish the operation parameters of the SGFET and investigate the influence of downscaling on both DC and AC characteristics. This will be done via the use of commercially available TCAD models such as Medici and Taurus (from Synopsis).In the second stage we will compare the operation of the novel SGFET with current FET technology such as fully-depleted FETs on SOI (FDSOI) and the finFET, also defined on SOI. This comparison, both for analog and digital applications, will be based on precisely defined benchmarking parameters.Finally we will evaluate critically the impact of the chosen mobility models on the operation of the devices. This will be done by introducing Monte Carlo generated mobility models into the TCAD environment that will enable a better electric field dependency of the carrier mobility in the 3D stucture.The result of this TCAD modelling will establish if the proposed 3D planar SGFET on SOI is a competitor for current novel FET structures structures such as finFETs and FDSOI MOSFETs. It will also establish the application domains in which the SGFET might outperform the current novel hightech devices. These domains can be analog and/or digital and low and/or full power applications.A positive outcome of the benchmarking exercise will prolong the lifetime of CMOS technology by 1) relaxing the need for agressive downscaling and 2) by disconnecting the geometry involved in downscaling from the parameters that lead to the deterioration of the device operation.