Semi-insulating Silicon substrates for high frequency integrated circuits

半绝缘硅衬底将非常有吸引力，因为它们将为射频和单片微波集成电路提供非常低的吸收衬底。两位研究人员先前从理论上分析了不同深层杂质对硅电阻率的影响，并表明电阻率接近100欧姆。Cm应通过掺杂补偿来实现。这一理论工作得到了我们最近发表的实验可行性研究的支持，该研究提供了一个非常有希望的电阻率值为12kohm。cm采用Mn作为深层杂质。本课题旨在研究高频集成电路用高电阻率硅衬底的科学与工程。该团队包括深层杂质的材料科学（牛津大学），高频硅器件的物理和技术（南安普顿大学），硅晶圆生长（MEMC）以及高频集成电路的设计和制造（Zarlink）方面的专业知识。该项目旨在更好地了解适当深层杂质（包括Mn）的扩散和掺杂与电阻率的关系，从而最大化硅柄晶圆的电阻率。由深层杂质引起的污染问题将通过研究扩散屏障和开发一种利用某些深层杂质的高扩散率的后端处理方法来解决。最近将铜金属化纳入后端硅生产过程表明，其他深层杂质不会被工业视为后端加工中的主要污染问题。最后，将在半绝缘硅衬底上制作SOI晶圆，并进行详细的高频表征。

Semi-insulating silicon substrates would be very attractive as handle wafers in Silicon On Insulator (SOI) technologies because they would provide very low-absorption substrates for RF and monolithic microwave integrated circuits. Two of the investigators have previously theoretically analysed the effect of different deep level impurities on silicon resistivity and shown that a resistivity of nearly 100kOhm.cm should be achievable by dopant compensation. This theoretical work has been supported by our recently published experimental feasibility study that has delivered a very promising resistivity value of 12kohm.cm using Mn as the deep level impurity. This proposal aims to study the science and engineering of high resistivity silicon substrates for high frequency integrated circuits. The team encompasses expertise on the materials science of deep level impurities (University of Oxford), on the physics and technology of high frequency silicon devices (University of Southampton), on silicon wafer growth (MEMC) and on the design and fabrication of high frequency integrated circuits (Zarlink). The project aims to better understand the diffusion and doping vs resistivity relations of appropriate deep level impurities (including Mn), and hence to maximise the resistivity of the silicon handle wafer. Contamination issues arising from the deep level impurities will be addressed by investigating diffusion barriers and also by developing a back-end processing approach that takes advantage of the high diffusivity of some deep level impurities. The recent incorporation of Cu metallization into back-end silicon production processes suggests that other deep level impurities would not be seen by industry as a major contamination issue in back-end processing. Finally, SOI wafers will be fabricated on semi-insulating silicon substrates and detailed high frequency characterisation carried out.