Semi-insulating Silicon substrates for high frequency integrated circuits

高频集成电路用半绝缘硅衬底

• 批准号: EP/F035721/1
• 负责人: Peter Wilshaw
• 金额: $ 35.03万
• 依托单位: University of Oxford
• 依托单位国家: 英国
• 项目类别: Research Grant
• 财政年份: 2008
• 资助国家: 英国
• 起止时间: 2008 至 无数据
• 项目状态: 已结题
• 来源: https://gtr.ukri.org/projects?ref=EP%2FF035721%2F1
• 关键词: Semi; insulating; Silicon; substrates; frequency

Semi-insulating silicon substrates would be very attractive as handle wafers in Silicon On Insulator (SOI) technologies because they would provide very low-absorption substrates for RF and monolithic microwave integrated circuits. Two of the investigators have previously theoretically analysed the effect of different deep level impurities on silicon resistivity and shown that a resistivity of nearly 100kOhm.cm should be achievable by dopant compensation. This theoretical work has been supported by our recently published experimental feasibility study that has delivered a very promising resistivity value of 12kohm.cm using Mn as the deep level impurity. This proposal aims to study the science and engineering of high resistivity silicon substrates for high frequency integrated circuits. The team encompasses expertise on the materials science of deep level impurities (University of Oxford), on the physics and technology of high frequency silicon devices (University of Southampton), on silicon wafer growth (MEMC) and on the design and fabrication of high frequency integrated circuits (Zarlink). The project aims to better understand the diffusion and doping vs resistivity relations of appropriate deep level impurities (including Mn), and hence to maximise the resistivity of the silicon handle wafer. Contamination issues arising from the deep level impurities will be addressed by investigating diffusion barriers and also by developing a back-end processing approach that takes advantage of the high diffusivity of some deep level impurities. The recent incorporation of Cu metallization into back-end silicon production processes suggests that other deep level impurities would not be seen by industry as a major contamination issue in back-end processing. Finally, SOI wafers will be fabricated on semi-insulating silicon substrates and detailed high frequency characterisation carried out.

在绝缘体上硅(SOI)技术中，半绝缘硅衬底将是非常有吸引力的手柄晶片，因为它们将为射频和单片微波集成电路提供非常低吸收的衬底。其中两名研究人员此前曾从理论上分析了不同深能级杂质对硅电阻率的影响，并证明了通过掺杂补偿应该可以达到近100kOhm.cm的电阻率。这项理论工作得到了我们最近发表的实验可行性研究的支持，该研究以锰作为深能级杂质，得到了非常有希望的12kohm.cm的电阻率值。这项建议旨在研究高频集成电路用高阻硅衬底的科学和工程。该团队拥有深能级杂质材料科学(牛津大学)、高频硅器件物理和技术(南安普顿大学)、硅晶片生长(MEMC)以及高频集成电路(Zarlink)设计和制造方面的专业知识。该项目旨在更好地了解适当的深能级杂质(包括锰)的扩散和掺杂与电阻率的关系，从而最大化硅手柄晶片的电阻率。深能级杂质引起的污染问题将通过调查扩散障碍和开发利用一些深能级杂质的高扩散性的后端处理方法来解决。最近将铜金属化纳入后端硅生产工艺表明，其他深层杂质不会被行业视为后端加工中的主要污染问题。最后，将在半绝缘硅衬底上制作SOI晶片，并进行详细的高频特性测试。