Exploring advanced technologies and architectures for massevely parallel processing systems based on networks-on-chip

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Technology scaling will allow Systems-on-Chip (SoCs) containing hundreds of complex cores in the nearfuture. These systems are omnipresent in different niche market such as portable/wireless, broadband, Internetswitching, mass storage, consumer products, and computers and automotive. A promising approach to design flexible high performance SoC architectures is to organize them as multiprocessors, where the ability for processors to communicate effectively with each other is critical. Tomorrow's on-chip bandwidth requirements will reach several hundreds of Gbit/s. Nowadays, buses are widely used, but they are increasingly becoming system bottlenecks as their bandwidth is usually shared between several modules, and are thus hard to scale. A significant challenge with future highly parallel SoCarchitectures is to avoid communications being their system bottleneck. Networks on Chip (NoCs) have beenproposed as a means to address these issues of achieving the communication infrastructure for SoC withhundred of computational cores. NoCs attempt to meet the requirements for future SoCs with respect toreusability, scalability, parallelism and fault tolerance. Furthermore, SoCs are presently the main drivers for theconvergence of multiple technologies (e.g. optical, mechanical, electrical, etc.), this promising more efficientparallel architectures. Thus, integrated optical networks are considered as an interesting alternative totraditional interconnects. In this context, the main objective of this project is to explore three domains that will allow meeting these requirements: 1) explore advanced architectures for NoC, 2) explore optical technology for next generation ofNoC and 3) perform and compare mapping on parallel systems-on-chip based on the advanced NoCsarchitecture proposed in 1) and 2).