Efficient architectures for wireless communications

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Multicarrier (MC) modulation is present in several standards for wireless communications systems (e.g. 802.11, 802.16) and is being considered for future wideband mobile systems. In this proposal, we will study the combination of MC modulation and low density parity check (LDPC) codes, particularly from an efficient VLSI implementation point of view. LDPC codes have been incorporated or are being considered for incorporation in several wireless communications standards. New codes are being proposed for various transmission conditions. The objectives of the proposed research are to continue our investigation on highly parallel structures and study how these can be combined efficiently with MC modulations. Of particular interest are the considerations of peak-to-average-power-ratio (PAPR), adaptive modulation and variable-rate and rate-compatible codes. To achieve these objectives, we will develop new architectures for LDPC codes, suitable for efficient implementations (e.g. using a small amount of resources and being fast) and able to achieve the data rate goals of future wideband access systems (i.e. 100's of Mbps to Gbps, depending on mobility). In parallel, we will also search for new LDPC codes that can offer good performance-complexity trade-offs. We will conduct extensive analytical studies and computer simulations. Some of our simulations will be done using "hardware-in-the-loop" techniques in order to diminish simulation time and consider implementation issues. For example, field programmable gate arrays (FPGA) circuits available in our laboratory, will be extensively used. This project will provide useful results that can be transferred to Canadian industry, helping Canada to be a major player in defining future wireless systems. Wideband wireless systems will be prevalent in the coming years and it is very important to train highly qualified personnel in this area.