Novel methodologies for fast electromagnetic modeling of signal propagation on interconnects

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The continuously increasing demand for higher functionality and lower cost of consumer and industrial electronics stipulates the evolution in microsystem design methodologies. As microsystem designs are exhibiting higher data exchange rates and tighter component integration, the modeling techniques must be changed adequately to account for the occurrence of tighter physical coupling between the devices. Thus, the large fragments of the microsystem designs must be modeled simultaneously while maintaining the electromagnetic accuracy of analysis. To overcome the constraints imposed on the analysis by the use of simplified traditional approaches capable of modelling only small microsystem fragments, we propose to develop a new generation of prototyping methodologies which can expediently handle the associated computational complexity. These methodologies will adapts today's fastest methods of computational electromagnetics to modeling of integrated electronics and map them onto powerful high-performance supercomputing architechtures. The main thrust of research will be in generalizing the recently proposed well-conditioned integral formulation to the case of multilayered substrates, augmenting them with skin-effect inclusive current flow models, and porting thus created algorithmic framework to the multiprocessor machines. This specialized software-hardware synergy will allow electronics designers to conduct electromagnetic modeling of integrated circuts of unprecedented sizes and complexity. Such modeling methods are expected to be adopted by the electronic design automation industry and establish a new standard as the available commercial tools greatly lack the capicity to address the associated complexity. The proposed research program will help close the gap between the needs and capabilities of electronics designers and has a potential to cut the multi-billion dollar losses incured by the majority of today's design houses and semiconductor foundries due to costly re-designs and delayed time-to-market.