A radiation hardened matrix computational module (MCM) for self-healing Field Programmable Gate Array (FPGA)

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Due to the increasing miniaturization of electronic circuits, the effect of radiation on electronic circuits deployed in space and in Earth orbit is a growing concern for satellite telecommunications organizations, such as Magellan Aerospace. Satellites have on board computers which use Field Programmable Gate Array (FPGA) technology, microprocessors, and application specific integrated circuits. The FPGA and other electronic based computers are susceptible to a phenomenon called single event upset. Cosmic rays emanating from a source in space interact with the Earth's atmosphere and produce radiation in the form of showers of ionized particles. When the particles of these showers hit the substrate of a transistor (component of a memory element) within an FPGA, they deposit charge, which may cause a change in the stored value (bit value) in the associated memory element. Consequently, a software program running on the FPGA computer may malfunction, which may lead to: unsafe operating conditions; end of mission; unfruitful costly mission; and may even cause harm to individuals on-board or on-land. Most available radiation protection (hardening) systems are not able to provide 100% complete shielding against radiation and ionization. For example, FPGA manufacturers provide internal hardening options, and application developers may add fault tolerance algorithms to their software and hardware running on the FPGAs. However, due to energy efficiency, hardware real-estate, and economical constraints, the level of protection against radiation is limited. For instance, only one error can be corrected in memories, but multiple errors may occur due to the effects of radiation. To properly address the problem, mitigation techniques must be combined and applied at all levels, including cutting edge research techniques and the manufacturer supplied mitigation options. For a specific application, we propose to provide a plan to implement the manufacturer's mitigation techniques and hardware redundancy (TMR). In addition, and more