Advanced Frequency Synthesizer Design

先进的频率合成器设计

• 批准号: 452471-2013
• 负责人: Plett, Calvin
• 金额: $ 2.91万
• 依托单位: Carleton University
• 依托单位国家: 加拿大
• 项目类别: Collaborative Research and Development Grants
• 财政年份: 2014
• 资助国家: 加拿大
• 起止时间: 2014-01-01 至 2015-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=554890
• 关键词: Advanced; Frequency; Synthesizer; Design

In this research project, advanced frequency synthesis techniques will be explored. Recently, all digital phase-locked loops (ADPLLs) have attracted significant interest due to their small area, better immunity to external noise, simplicity of design, and scalability with process technology. However, the phase noise of the ADPLL typically falls short compared to conventional analog PLLs. Noise performance of the ADPLL is determined by phase granularity and resolution, non-linearity in the loop, and non-idealities of the loop components such as the phase detector and the oscillator. Improvements at the system level must be undertaken while ensuring that requirement of noise, settling time, frequency lock range, phase resolution and power consumption are met. Typically, calibration techniques are required to compensate for process, power-supply voltage, and temperature variations. In addition to noise, unwanted signals (spurs) which are often the result of nonlinearity and mismatch, have to be filtered out to prevent interference with desired signals. At the component level, each block must be designed to reduce non-idealities such noise and nonlinearity. The objective of this project is to explore new design techniques to improve the ADPLL while maintaining its excellent qualities and advantages. The main focus will be on improving the noise performance of the high-speed ADPLLs by employing new techniques both at the system level and at the component level. Working closely with our industrial partner will ensure that our design is practical and will fit in with their larger scale project. Having an improved ADPLL in their portfolio will strengthen their position as the world leader in this field. This is expected to have an impact on their portion of the global market share in this area, and by the successful introduction of related products, will potentially lead to more employment opportunities in Canada. Through publication of the technological advancements in this project, knowledge will be distributed throughout the academic community leading to international recognition for Carleton University and for the researchers involved, advancing the state-of-the-art of the design techniques used in this field.

在本研究项目中，将探索先进的频率合成技术。近年来，全数字锁相环（ADPLL）因其面积小、抗外部噪声能力强、设计简单、可扩展性好等优点而受到广泛关注。然而，与传统模拟PLL相比，ADPLL的相位噪声通常会下降福尔斯。ADPLL的噪声性能取决于相位粒度和分辨率、环路中的非线性度以及鉴相器和振荡器等环路组件的非理想性。必须在系统级进行改进，同时确保满足噪声、建立时间、频率锁定范围、相位分辨率和功耗的要求。通常，需要校准技术来补偿工艺、电源电压和温度变化。除了噪声之外，通常由非线性和失配导致的不需要的信号（杂散）必须被滤除，以防止干扰所需信号。在元件级，每个模块都必须设计为减少非理想性，如噪声和非线性。本计画的目的是探讨新的设计技术，以改善全数字锁相回路，同时保持其优良的品质与优点。主要的重点将是通过在系统级和元件级采用新技术来提高高速ADPLL的噪声性能。与我们的工业合作伙伴密切合作将确保我们的设计是实用的，并将适合他们的大型项目。在他们的产品组合中拥有改进的ADPLL将加强他们作为该领域世界领导者的地位。预计这将对他们在这一领域的全球市场份额产生影响，并通过成功推出相关产品，可能会在加拿大带来更多的就业机会。通过出版该项目的技术进步，知识将在整个学术界传播，从而为卡尔顿大学和相关研究人员带来国际认可，推进该领域最先进的设计技术。