Advanced Frequency Synthesizer Design

本研究计划将探讨先进的频率合成技术。最近，所有数字锁相环（adpll）由于其面积小，对外部噪声具有更好的抗扰性，设计简单以及工艺技术的可扩展性而引起了极大的兴趣。然而，与传统模拟锁相环相比，ADPLL的相位噪声通常较低。ADPLL的噪声性能取决于相位粒度和分辨率、环路中的非线性以及环路元件（如鉴相器和振荡器）的非理想性。必须在系统层面进行改进，同时确保满足噪声、稳定时间、频率锁定范围、相位分辨率和功耗的要求。通常，需要校准技术来补偿工艺、电源电压和温度变化。除了噪声，不需要的信号（杂散）往往是非线性和不匹配的结果，必须过滤掉，以防止干扰所需的信号。在元件级，必须设计每个块以减少非理想性，如噪声和非线性。本项目的目的是探索新的设计技术，以提高ADPLL的性能，同时保持其优良的品质和优势。本文的重点是通过在系统级和元件级采用新技术来改善高速adpll的噪声性能。与我们的工业合作伙伴密切合作将确保我们的设计是实用的，并将适合他们的更大规模的项目。在他们的产品组合中有一个改进的ADPLL将加强他们在该领域的世界领先地位。预计这将对他们在这一领域的全球市场份额产生影响，并通过成功引入相关产品，将有可能在加拿大带来更多的就业机会。通过该项目的技术进步的出版，知识将在整个学术界传播，从而为卡尔顿大学和相关研究人员带来国际认可，推进该领域使用的最先进的设计技术。

In this research project, advanced frequency synthesis techniques will be explored. Recently, all digital phase-locked loops (ADPLLs) have attracted significant interest due to their small area, better immunity to external noise, simplicity of design, and scalability with process technology. However, the phase noise of the ADPLL typically falls short compared to conventional analog PLLs. Noise performance of the ADPLL is determined by phase granularity and resolution, non-linearity in the loop, and non-idealities of the loop components such as the phase detector and the oscillator. Improvements at the system level must be undertaken while ensuring that requirement of noise, settling time, frequency lock range, phase resolution and power consumption are met. Typically, calibration techniques are required to compensate for process, power-supply voltage, and temperature variations. In addition to noise, unwanted signals (spurs) which are often the result of nonlinearity and mismatch, have to be filtered out to prevent interference with desired signals. At the component level, each block must be designed to reduce non-idealities such noise and nonlinearity. The objective of this project is to explore new design techniques to improve the ADPLL while maintaining its excellent qualities and advantages. The main focus will be on improving the noise performance of the high-speed ADPLLs by employing new techniques both at the system level and at the component level. Working closely with our industrial partner will ensure that our design is practical and will fit in with their larger scale project. Having an improved ADPLL in their portfolio will strengthen their position as the world leader in this field. This is expected to have an impact on their portion of the global market share in this area, and by the successful introduction of related products, will potentially lead to more employment opportunities in Canada. Through publication of the technological advancements in this project, knowledge will be distributed throughout the academic community leading to international recognition for Carleton University and for the researchers involved, advancing the state-of-the-art of the design techniques used in this field.