Advanced frequency synthesizer design

先进的频率合成器设计

• 批准号: 507688-2016
• 负责人: Plett, Calvin
• 金额: $ 2.28万
• 依托单位: Carleton University
• 依托单位国家: 加拿大
• 项目类别: Collaborative Research and Development Grants
• 财政年份: 2017
• 资助国家: 加拿大
• 起止时间: 2017-01-01 至 2018-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=618744
• 关键词: Advanced; frequency; synthesizer; design

This research project involves the exploration of advanced frequency synthesis techniques, while also considering applications in timing recovery circuits for broadband data communications systems. The trend recently has been to move away from analog and towards all digital phase-locked loops (ADPLLs), due to their small area, better immunity to external noise, simplicity of design, and scalability with process technology. The main challenge to be addressed in this proposal is the improvement in phase noise of the ADPLL. Noise performance of the ADPLL is determined by phase granularity and resolution, determined by the loop characteristics, non-linearity in the loop, and non-idealities of the loop components such as the phase detector and the oscillator. At the system level, studies will be undertaken to ensure that requirement of frequency bands and lock range, noise, settling time, phase resolution and power consumption are met and will fit in with the objectives of the industrial collaborators. In addition to noise, unwanted signals (spurs) which are often the result of nonlinearity and mismatch will have to be minimized to reduce interference with desired signals. At the component level, each sub-block circuit will be designed to reduce non-idealities such as noise and nonlinearity. The research will build on previous work done both at the system level and at the component level. Continuing to work closely with our industrial partner will ensure that our design is practical and will fit in with their larger scale project. Having an improved ADPLL with applications to both frequency synthesizers and clock and data recovery circuits in their portfolio will strengthen their position as a world leader in this field. This is expected to have an impact on their portion of the global market share in this area, and by the successful introduction of related products, will potentially lead to more employment opportunities in Canada. Through publication of the technological advancements in this project, knowledge will be distributed throughout the academic community leading to international recognition for Carleton University and for the researchers involved, advancing the state-of-the-art of the design techniques used in this field.

本研究项目包括探索先进的频率合成技术，同时也考虑在宽带数据通信系统的时序恢复电路中的应用。最近的趋势是从模拟转向全数字锁相环（adpll），因为它们面积小，对外部噪声具有更好的抗扰性，设计简单，并且具有工艺技术的可扩展性。该方案需要解决的主要问题是如何改善ADPLL的相位噪声。ADPLL的噪声性能由相位粒度和分辨率决定，由环路特性、环路中的非线性和环路元件（如鉴相器和振荡器）的非理想性决定。在系统层面，将进行研究，以确保满足频段和锁定范围、噪音、稳定时间、相位分辨率和功耗的要求，并符合工业合作伙伴的目标。除了噪声之外，通常由非线性和不匹配引起的不需要的信号（杂散）必须最小化，以减少对所需信号的干扰。在元件级，每个子块电路将被设计以减少非理想性，如噪声和非线性。这项研究将建立在以前在系统级和组件级所做的工作的基础上。继续与我们的工业合作伙伴密切合作，将确保我们的设计是实用的，将适合他们的更大规模的项目。在他们的产品组合中，有一个改进的ADPLL应用于频率合成器和时钟和数据恢复电路，将加强他们在该领域的世界领先地位。预计这将对他们在这一领域的全球市场份额产生影响，并通过成功引入相关产品，将有可能在加拿大带来更多的就业机会。通过该项目的技术进步的出版，知识将在整个学术界传播，从而为卡尔顿大学和相关研究人员带来国际认可，推进该领域使用的最先进的设计技术。