Advanced methodologies and computer aided design tools for signal integrity analysis of high-speed circuits and systems

近年来，对高频和微型设计的强烈驱动一直处于微电子、通信和计算系统的仿真和验证方法新发展的前沿。设计要求变得非常严格，要求更高的工作速度，更尖锐的激励，更密集的布局和低功耗。因此，电路/EM/机械和热设计考虑之间的传统界限正在迅速消失。如果在设计阶段没有正确解决串扰和衰减等高速效应，可能会导致逻辑毛刺，使制造的数字电路无法工作，或者它们可能会使模拟信号失真，使其无法满足规格。为了解决上述困难，提出了一个新的研究计划，包括以下举措，以开发针对高速模块的新一代计算机辅助工具和方法：（a）开发快速/准确的信号和电源完整性分析工具，（B）开发以信号完整性为重点的并行电路模拟和优化工具;（c）混合域和多域计算机辅助设计工具和方法纪律分析。 拟议的研究计划侧重于战略问题，以推进高速应用和广泛的电子设计水平的各个方面的最新技术。拟议研究的影响将是促进新一代多学科工具的开发，用于并行分析和验证高速模块，包括所有级别的设计层次，如片上，多芯片模块，互连，封装和印刷电路板。最后，需要注意的是，设计自动化算法效率的提高间接地缩短了新产品的设计周期，从而实现了进一步的创新，导致更多的新电子和通信产品涌入我们的市场，最终导致更健康的经济。

During the recent years, the intense drive for high-frequency and miniature designs has been at the forefront of new developments in simulation and verification methodologies focused on microelectronics, communication and computing systems. The design requirements are becoming very stringent, demanding higher operating speeds, sharper excitations, denser layouts and low power consumption. Consequently, traditional boundaries between the circuit/EM/mechanical and thermal design considerations are rapidly vanishing. High-speed effects such as crosstalk and attenuation, if not addressed properly during the design stage, can cause logic glitches which render a fabricated digital circuit inoperable, or they can distort an analog signal such that it fails to meet specifications. To address the above difficulties, a new research program with following initiatives is proposed to develop new-generation computer-aided tools and methodologies targeting high-speed modules: (a) Development of fast/accurate signal and power integrity analysis tools, (b) Development of parallel circuit simulation and optimization tools with emphasis on signal integrity and (c) Computer-aided design tools and methodologies for mixed-domain and multi-disciplinary analysis. The proposed research program is focused on strategic issues, to advance the state-of-the art in various aspects of high-speed applications and wide range of electronic design levels. The impact of the proposed research would be to facilitate the development of new generation multidisciplinary tools for concurrent analysis and validation of high-speed modules encompassing all levels of design hierarchy, such as on-chip, multi-chip modules, interconnects, packages and printed circuit boards. Finally, it is to be duly noted that an improved efficiency of design automation algorithms indirectly percolates in decreasing the design cycle time of new products, enabling further innovation leading to an increased influx of new electronic and communication products entering our markets, ultimately resulting in a healthier economy.