Hardware Acceleration Technologies Enabling Polynomial System Solving

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Hardware acceleration technologies (multicore processors, graphics processing units, field-programmable gate arrays) provide vast opportunities for innovation in scientific computing. For instance, general- -purpose computation on graphics hardware now allows several types of calculations (simulation, data analysis, etc.) to satisfy the constraints of real time computing. At the same time, the pervasive ubiquity and diversity of parallel architectures creates major challenges for scientists and engineers. On the scientific side, this situation leads to a quest for algorithms and software capable of exploiting the various levels of parallelism, from hardware acceleration technologies to clusters. On the software engineering side, techniques for adapting legacy code and supporting the new hardware are in demand. This proposal aims at developing techniques that will permit mathematical software to take the best advantage of parallel architectures and hierarchical memories. Our focus is on graphics processing units and their support to polynomial system solvers for which specific features (intermediate expression swell, irregular data patterns) make this proposal even more challenging. The proposed research program comprises three projects which cover theoretical aspects, algorithms, software implementation and applications of those.