Hardware Acceleration Technologies Enabling Polynomial System Solving

硬件加速技术（多核处理器、图形处理单元、现场可编程门阵列）为科学计算的创新提供了巨大的机会。例如，图形硬件上的通用计算现在允许几种类型的计算（模拟、数据分析等）来满足实时计算的约束。与此同时，并行架构的普遍性和多样性给科学家和工程师带来了重大挑战。在科学方面，这种情况导致了对能够利用各种并行性级别的算法和软件的追求，从硬件加速技术到集群。在软件工程方面，需要适应遗留代码和支持新硬件的技术。本提案旨在开发技术，使数学软件能够充分利用并行架构和分层存储器。我们的重点是图形处理单元及其对多项式系统解算器的支持，而多项式系统解算器的特定特征（中间表达式膨胀、不规则数据模式）使该建议更具挑战性。本研究计划分为理论、算法、软件实现及应用三个方面。

Hardware acceleration technologies (multicore processors, graphics processing units, field-programmable gate arrays) provide vast opportunities for innovation in scientific computing. For instance, general--purpose computation on graphics hardware now allows several types of calculations (simulation, data analysis, etc.) to satisfy the constraints of real time computing. At the same time, the pervasive ubiquity and diversity of parallel architectures creates major challenges for scientists and engineers. On the scientific side, this situation leads to a quest for algorithms and software capable of exploiting the various levels of parallelism, from hardware acceleration technologies to clusters. On the software engineering side, techniques for adapting legacy code and supporting the new hardware are in demand.This proposal aims at developing techniques that will permit mathematical software to take the best advantage of parallel architectures and hierarchical memories. Our focus is on graphics processing units and their support to polynomial system solvers for which specific features (intermediate expression swell, irregular data patterns) make this proposal even more challenging. The proposed research program comprises three projects which cover theoretical aspects, algorithms, software implementation and applications of those.