Next-generation programmable logic devices: improving silicon efficiency and designer productivity

在最新的制造技术中，一个晶体管的长度只有28纳米，一个计算机芯片上可以容纳50亿个晶体管。这种令人难以置信的晶体管密度实现了前所未有的处理，但随之而来的是一个重大的经济挑战--设计和制造一个28纳米芯片的成本超过6000万美元。很少有市场大到足以证明定制的、单一用途的计算机芯片的成本是合理的，所以越来越多的芯片必须高度可编程，才能瞄准足够大的市场，从而在经济上可行。 一种高度可编程的芯片是现场可编程门阵列(FPGA)。在现场可编程门阵列中，大量的可编程功能块通过可编程布线连接。每个功能块执行的处理可以通过加载不同的“配置位”来改变，并且块之间的连接是由基于可编程晶体管的开关而不是固定导线来实现的。这两种形式的可重编程性结合在一起，允许在FPGA中实现任何电路，而不需要设计和制造定制芯片。现场可编程门阵列已经成为非常重要的设备，年销售额超过50亿美元，并在从高端通信设备到儿童电子游戏的不同市场中使用。 FPGA的可重编程性是有代价的；与定制芯片中的电路相比，FPGA中的电路更大、更慢、更耗电。本研究试图通过寻找新的使其在关键领域更高效的功能块来使其在诸如无线通信系统等关键应用中更高效。这项研究的另一个方面是寻找方法，通过这些方法可以将FPGA的功率降低到适合于电池供电的设备使用的程度。最后，要在现场可编程门阵列中实现设计，需要一种计算机辅助设计(CAD)工具，该工具可以将工程师对电路的描述转换为配置现场可编程门阵列以执行该功能的数百万个编程位。随着现场可编程门阵列容量的增加，CAD工具要在合理的处理时间内高效地实现越来越大的设计变得更加困难；我们试图解决这一不足，以保持现场可编程门阵列设计人员的工作效率。

In the latest manufacturing technology the length of a transistor is only 28 nm and 5 billion transistors will fit on a single computer chip. This incredible transistor density enables unprecedented processing, but comes with a major economic challenge -- it costs over $60M to design and manufacture a 28 nm chip. Few markets are large enough to justify the cost of a custom, single-purpose computer chip, so increasingly chips must be highly programmable to target a large enough market to be economically viable. One type of highly programmable chip is a Field Programmable Gate Array (FPGA). In FPGAs, a large number of programmable function blocks are connected by programmable routing. The processing performed by each function block can be changed by loading different "configuration bits", and the connections between blocks are made by programmable transistor-based switches, rather than fixed wires. Together these two forms of reprogrammability allow any circuit to be implemented in an FPGA, without the design and manufacture of a custom chip. FPGAs have become very important devices with sales of over $5 billion/year, and usage in diverse markets from high-end communications equipment to children's electronic games. FPGA reprogrammability comes at a cost; circuits in FPGAs are larger, slower and more power-hungry than those in a custom chip. This reserach seeks to make FPGAs more efficient for their key applications, such as wireless communication systems, by finding new FPGA function block that make them more efficient in these key domains. Another aspect of this research seeks methods by which FPGA power can be reduced to the point that they are suitable for use in battery-operated devices. Finally, to implement a design in an FPGA requires a sophicated Computer-Aided Design (CAD) tool which can transform an engineer's description of a circuit into the millions of programming bits that configure the FPGA to perform that function. As FPGA capacity increases it becomes more difficult for CAD tools to implement ever-larger designs efficiently and in a reasonable processing time; we seek to address this shortfall to keep FPGA designers productive.