Next-generation programmable logic devices: improving silicon efficiency and designer productivity

下一代可编程逻辑器件：提高芯片效率和设计人员生产力

• 批准号: 403299-2011
• 负责人: Betz, Vaughn
• 金额: $ 1.6万
• 依托单位: University of Toronto
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2015
• 资助国家: 加拿大
• 起止时间: 2015-01-01 至 2016-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=573380
• 关键词: Next; generation; programmable; logic; devices

In the latest manufacturing technology the length of a transistor is only 28 nm and 5 billion transistors will fit on a single computer chip. This incredible transistor density enables unprecedented processing, but comes with a major economic challenge -- it costs over $60M to design and manufacture a 28 nm chip. Few markets are large enough to justify the cost of a custom, single-purpose computer chip, so increasingly chips must be highly programmable to target a large enough market to be economically viable. One type of highly programmable chip is a Field Programmable Gate Array (FPGA). In FPGAs, a large number of programmable function blocks are connected by programmable routing. The processing performed by each function block can be changed by loading different "configuration bits", and the connections between blocks are made by programmable transistor-based switches, rather than fixed wires. Together these two forms of reprogrammability allow any circuit to be implemented in an FPGA, without the design and manufacture of a custom chip. FPGAs have become very important devices with sales of over $5 billion/year, and usage in diverse markets from high-end communications equipment to children's electronic games. FPGA reprogrammability comes at a cost; circuits in FPGAs are larger, slower and more power-hungry than those in a custom chip. This reserach seeks to make FPGAs more efficient for their key applications, such as wireless communication systems, by finding new FPGA function block that make them more efficient in these key domains. Another aspect of this research seeks methods by which FPGA power can be reduced to the point that they are suitable for use in battery-operated devices. Finally, to implement a design in an FPGA requires a sophicated Computer-Aided Design (CAD) tool which can transform an engineer's description of a circuit into the millions of programming bits that configure the FPGA to perform that function. As FPGA capacity increases it becomes more difficult for CAD tools to implement ever-larger designs efficiently and in a reasonable processing time; we seek to address this shortfall to keep FPGA designers productive.

在最新的制造技术中，晶体管的长度只有28纳米，50亿个晶体管将适合一个计算机芯片。这种令人难以置信的晶体管密度实现了前所未有的处理，但也带来了重大的经济挑战-设计和制造28纳米芯片的成本超过6000万美元。很少有市场大到足以证明定制的、单一用途的计算机芯片的成本是合理的，因此越来越多的芯片必须是高度可编程的，以瞄准足够大的市场，从而在经济上可行。 一种类型的高度可编程芯片是现场可编程门阵列（FPGA）。在FPGA中，大量的可编程功能块通过可编程布线连接。每个功能块执行的处理可以通过加载不同的“配置位”来改变，块之间的连接是由基于可编程晶体管的开关，而不是固定的电线。这两种形式的可重编程性一起允许在FPGA中实现任何电路，而无需设计和制造定制芯片。FPGA已成为非常重要的设备，销售额超过50亿美元/年，并在从高端通信设备到儿童电子游戏的各种市场中使用。 FPGA的可重编程性是有代价的; FPGA中的电路比定制芯片中的电路更大、更慢、更耗电。本研究旨在通过寻找新的FPGA功能块，使FPGA在这些关键领域（如无线通信系统）中更有效，从而使FPGA在这些关键领域中更有效。本研究的另一个方面是寻求将FPGA功耗降低到适合在电池供电设备中使用的方法。最后，在FPGA中实现设计需要一个复杂的计算机辅助设计（CAD）工具，它可以将工程师对电路的描述转换为数百万个编程位，这些位配置FPGA以执行该功能。随着FPGA容量的增加，CAD工具越来越难以在合理的处理时间内有效地实现更大的设计;我们试图解决这一不足，以保持FPGA设计人员的生产力。