Exploiting and Enhancing Programmable Logic for Deep Learning and Datacenter Acceleration

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Computing has transformed society, enabling ubiquitous communications, on-demand entertainment, speech recognition, and more. While computation demand is growing for deep learning (DL) and other applications, the traditional efficiency gains afforded by transistor scaling are slowing down. To fill this gap, we need computational devices that are more efficient yet reprogrammable to allow new applications. Field-Programmable Gate Arrays (FPGAs) can be reprogrammed at the hardware level, enabling energy-efficiency gains of 10x or more vs. processors for many embedded and datacenter applications. We seek to advance on three related fronts: implementing efficient DL inference on FPGAs, architecting better reconfigurable devices and enhancing computer-aided design (CAD) tools to enable these new devices. Our first research thrust seeks more efficient DL inference on FPGAs while simultaneously creating productive development flows. In our heterogeneous pipeline (HPIPE) project, we leverage FPGA programmability by implementing customized hardware for every layer in a convolutional neural network (CNN) using a new domain specific compiler. Our neural processing unit (NPU) project instead creates DL functional units controlled by an instruction stream produced from software. Both projects have industry-leading performance, and we will enhance them in multiple ways, including scaling to multiple chips in parallel, exploiting the new tensor blocks in AI-optimized FPGAs, and combining the specialized units of HPIPE with the software programmability of the NPU. Our second thrust seeks new reconfigurable accelerator device (RAD) architectures to allow higher performance and easier development, particularly for DL and for datacenter infrastructure. We will investigate not only conventional 2D chips, but also the multi-die stacks enabled by recent technologies. We envision RADs that combine an FPGA fabric die on an infrastructure die containing coarse-grain programmable accelerators (such as hardened matrix-vector multiply units), large memory blocks, and an embedded network-on-chip (NoC) to link all the components. The combination of FPGA fabric and coarse-grained accelerators can increase performance, while the NoC decouples design components to simplify design. Our third thrust develops the computer-aided design (CAD) tools to investigate these RAD architectures and allow implementation of DL applications on them. First, we will develop a new tool (RADSim) to evaluate fabric, accelerator and NoC combinations by determining execution time for various applications on each architecture. Next, we will enhance the widely-used Versatile Place and Route (VPR) tool to co-optimize the placement of fabric resources, accelerator blocks and NoC routers, with latency and congestion estimates informed by RADsim. The open-source VPR tool is already enabling a wide variety of innovation and products, and these enhancements will make it still more capable.