Theory and Methodology for Performance-Driven Automation in RTL and Testbench Debugging

RTL 和测试台调试中性能驱动自动化的理论和方法

• 批准号: RGPIN-2014-04275
• 负责人: Veneris, Andreas
• 金额: $ 2.26万
• 依托单位: University of Toronto
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2015
• 资助国家: 加拿大
• 起止时间: 2015-01-01 至 2016-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=587707
• 关键词: Theory; Methodology; Performance; Driven; Automation

The semiconductor industry has products reaching all aspects of commercial and consumer markets domestically and internationally. It consistently creates smaller, faster and more powerful integrated computer Very Large Scale of Integration (VLSI) chips which fuel the accelerated demand of the end products. Chip companies are challenged to design increasingly complex devices while remaining cost competitive. Computer-Aided Design (CAD) tools are continuously improving their efficiency to mitigate this cost. In the past decade, the effort to verify the correctness of these systems has increased disproportionately and takes as much as 70% of the total design cycle, a trend coined the verification gap. This is also confirmed by the 3:1 ratio between the number of verification engineers versus that of designers in the semiconductor industry, a trend that has been projected to increase almost two-fold by 2015. When verification fails and the design is proven to be incorrect, debugging follows to identify the source of the error and fix it. Today, this is a predominantly manual task. As technical roadmaps and research studies indicate, the resource-intensive manual debugging has become the most significant component of the verification gap taking as much as 32% of the total verification time. That is, for a typical design cycle of 18 months, engineers today spend 4-5 months in manual debugging. Evidently, this introduces disproportional non-recurring costs and it may jeopardize the chip delivery day. Consequently, it comes as no surprise that debugging was recently pronounced the central theme in verification R&D for the next 5-6 years by the CEO of Synopsys, the largest Electronic Design Automation CAD tool vendor. Our group was the first to recognize this emerging trend ten years ago. In 2005 we proposed the first automated debugging theory and methodology that today is used and referenced by peer research groups and industry worldwide. In this proposal we leverage this investment to investigate new theories for formal CAD tools and respective methodologies for the modern chip verification/debug cycle. These tools will utilize robust engines and proprietary data mining algorithms to exhaustively analyze the big data generated by verification to ensure correctness of the design. The end result will be the theory and a CAD tool that can be deployed in any industrial semiconductor site to aid the engineers during debugging. This ambitious and multi-disciplinary project promises major theoretical advances and practical applications that instill benefit in CAD for VLSI but also in other fields of science such as software verification, data mining and artificial intelligence. Further, due to the continuous growth of semiconductor industry, there has been a shortage of Highly Qualified Personnel (HQP) in digital VLSI verification/debug that remains strong at all levels of education (PhD, MASc, BASc). Hence, it comes as no surprise that there continues to be much industrial, political and educational attention within Canada devoted in training of HQP in related areas. Everybody involved with the development of the technology will gain knowledge in advanced CAD concepts, practical VLSI verification, hands-on experience and strategic planning. Our pioneering R&D environment and collaboration with the industry will offer them an unparalleled experience in innovation. Graduate students will publish in prominent scientific conferences/journals with strict acceptance criteria and they will gain international visibility. As shown by the post-graduation employment success of our alumnus, this HQP will gain knowledge at the forefront of technology and they will exercise it in a way beneficial to the Canadian society and economy.

半导体行业的产品覆盖了国内外商业和消费市场的方方面面。它始终如一地创造出更小、更快、更强大的集成计算机超大规模集成(VLSI)芯片，从而推动了终端产品的加速需求。芯片公司面临的挑战是，在设计日益复杂的设备的同时，保持成本竞争力。计算机辅助设计(CAD)工具正在不断提高其效率，以降低这一成本。在过去的十年中，验证这些系统的正确性的努力不成比例地增加，占整个设计周期的70%，这一趋势导致了验证差距。半导体行业的验证工程师与设计师人数之比为3：1，这一趋势预计到2015年将增加近两倍，这也证实了这一点。当验证失败并且设计被证明是不正确的时，随后进行调试以确定错误的来源并修复它。如今，这主要是一项人工任务。技术路线图和研究表明，资源密集型人工调试已成为验证差距的最重要组成部分，占总验证时间的32%。也就是说，对于一个典型的18个月的设计周期，工程师现在需要花费4-5个月的时间进行手动调试。显然，这引入了不成比例的非经常性成本，并可能危及芯片交货日。因此，调试最近被最大的电子设计自动化CAD工具供应商Synopsys的首席执行官宣布为未来5-6年验证研发的中心主题就不足为奇了。 十年前，我们团队是第一个认识到这一新兴趋势的人。在2005年，我们提出了第一个自动化调试理论和方法，今天被世界各地的同行研究小组和行业使用和参考。在这份提案中，我们利用这笔投资来研究用于现代芯片验证/调试周期的正式CAD工具和相应方法的新理论。这些工具将利用强大的引擎和专有的数据挖掘算法，对验证产生的大数据进行详尽的分析，以确保设计的正确性。最终的结果将是理论和CAD工具，可以部署在任何工业半导体现场，以帮助工程师在调试期间。 这个雄心勃勃的多学科项目承诺了重大的理论进步和实际应用，这不仅有利于VLSI的CAD，而且还将在其他科学领域，如软件验证、数据挖掘和人工智能方面。此外，由于半导体行业的持续发展，数字VLSI验证/调试方面的高素质人才(HQP)一直短缺，而这些人员在各级教育(博士、硕士、BASC)中仍然很强大。因此，毫不奇怪，加拿大国内继续有很多工业、政治和教育方面的关注致力于相关领域的HQP培训。每个参与这项技术开发的人都将获得先进的CAD概念、实用的VLSI验证、实践经验和战略规划方面的知识。我们领先的研发环境和与行业的合作将为他们提供无与伦比的创新体验。研究生将在具有严格接受标准的著名科学会议/期刊上发表文章，他们将获得国际知名度。正如我们校友毕业后的就业成功所表明的那样，这位HQP将获得技术前沿的知识，他们将以一种有利于加拿大社会和经济的方式行使这些知识。